
4565B Ultramapper Full Transport Retiming Device
Hardware Design Guide, Revision 2
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
December 17, 2003
48
Agere Systems Inc.
6 Reference Clocks
Table 6-1. High-Speed Interface Input Clocks Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/
Max
Duty Cycle
RHSCP/N
6.43
155.52 MHz
20
—
0.4
0.4 nominal
50% ± 5%
THSCP/N
6.43
155.52 MHz
20
0.01 UIp-p or 64 psp-p or
0.001 UIrms (12 kHz—1.3 MHz)
0.4
0.4 nominal
50% ± 5%
THSCP/N
1.6
622.08 MHz
20
0.04 UIp-p or 64 psp-p
(12 kHz—5 MHz)
0.4
nom
0.6
max
—50% ± 5%
Table 6-2. Protection Link Input Clock Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/Max
Duty Cycle
RPSCP/N
6.43
155.52 MHz
20
—
0.4
nominal
50% ± 5%
Table 6-3. DS3/E3/STS-1 Input Clocks Specifications
Clock Name
Period
(ns)
Frequency Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/
Max
Duty Cycle
DS3DATAOUTCLK[6:1] (DS3) 22.353 44.736 MHz
20
0.05 UIp-p or
1.12 nsp-p
(10 kHz—400 kHz)
5
max
50% ± 10%
DS3DATAINCLK[6:1](DS3)
22.353 44.736 MHz
20
—
3.5
2.5
max
50% ± 5%
DS3DATAOUTCLK[6:1](E3)
29.090 34.368 MHz
20
0.03 UIp-p or
0.87 nsp-p
(100 kHz—800 kHz)
5
max
50% ± 10%
DS3DATAINCLK[6:1]](E3)
29.090 34.368 MHz
20
—
3.5
2.5
max
50% ± 5%
DS3DATAOUTCLK[6:1](STS-1) 19.290 51.84 MHz
20
0.01 UIp-p or
0.19 nsp-p or
0.001 UIrms
(12 kHz—400 kHz)
5
max
50% ± 10%
DS3DATAINCLK[6:1](STS-1)
19.290 51.84 MHz
20
—
3.5
2.5
max
50% ± 5%
Table 6-4. DS1/E1 DJA Input Clocks Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/Max
Duty Cycle
E1XCLK
15.25
65.536 MHz
50
0.1 UIp-p or 1.5 nsp-p
(20 kHz—100 kHz)
3.5
Max
50% ± 10%
DS1XCLK
20.20
49.408 MHz
32
0.1 UIp-p or 2.0 nsp-p
(10 kHz—40 kHz)
3.5
Max
50% ± 10%
E1XCLK
30.52
32.768 MHz
50
0.1 UIp-p or 3.0 nsp-p
(20 kHz—100 kHz)
3.5
Max
50% ± 10%
DS1XCLK
40.40
24.704 MHz
32
0.1 UIp-p or 4.0 nsp-p
(10 kHz—40 kHz)
3.5
Max
50% ± 10%