參數(shù)資料
型號(hào)： 4565B2
廠商： LSI CORP
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 20/61頁(yè)
文件大?。?/td> 1691K
代理商： 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
27
Table 2-17. Reference Clocks
Pin
Symbol
Type
Name/Description
V8
DS2AISCLK
I pd
DS2 AIS Clock. See separate DS2/E2 application note for use in DS2 mode. If used,
this input can be provided by a free-running crystal or clocking chip.
AA1
E2AISCLK
I pd
E2 AIS Clock. See separate DS2/E2 application note for use in E2 mode. If used, this
input can be provided by a free-running crystal or clocking chip.
AM18
E1XCLK
I pd
E1 X Clock. This clock signal is used for three purposes: to generate E1 AIS (all 1s), as
a reference to the E1 DJA, and as a clock source for the test pattern generator and test
pattern monitor. This input may be provided by a 2.048 MHz, a 32.768 MHz, or a
65.536 MHz ± 50 ppm free-running crystal oscillator or clocking chip.
Note: For the E1 DJA, an input of 32.768 MHz or 65.536 MHz must be used.
AP21
DS1XCLK
I pd
DS1 X Clock. This clock signal is used for three purposes: to generate DS1 AIS (all
1s), as a reference to the DS1 DJA, and as a clock source for the test pattern generator
and test pattern monitor. This input may be provided by a 1.544 MHz, a 24.704 MHz, or
a 49.408 MHz ± 32 ppm free-running crystal oscillator or clocking chip.
Note: For the DS1 DJA, an input of 24.704 MHz or 49.408 MHz must be used.
E19
DS3XCLK
I pd
DS3 X Clock. A 44.736 MHz ± 20 ppm clock input for DS3 DJA and TPG. This input
may be provided by a 44.736 MHz ± 20 ppm free-running crystal oscillator or clocking
chip.
H18
E3XCLK
I pd
E3 X Clock. A 34.368 MHz ± 20 ppm clock input for E3 DJA and TPG. This input may
be provided by a 34.368 MHz ± 20 ppm free-running crystal oscillator or clocking chip.
Table 2-18. Low-Order Path Overhead Access, Transmit Direction
Pin
Symbol
Type
Name/Description
B22
LOPOHCLKIN
I pd
Low-Order Path Overhead Clock. 19.44 MHz clock supplied from external cir-
cuits that provide the low-order path overhead data.
D20
LOPOHDATAIN
I pd
Low-Order Path Overhead Data. The following parts of the low-order (VT)
overhead are presented at this pin: communication channel bits (O bits), V5, J2,
Z6/N2, Z7, and K4 byte.
E20
LOPOHVALIDIN
I pd
Low-Order Path Overhead Data Input Valid. This signal is a mask, which indi-
cates the location of the overhead bytes in the LOPOHDATAIN.
Table 2-19. Low-Order Path Overhead Access, Receive Direction
Pin
Symbol
Type
Name/Description
A21
LOPOHCLKOUT
O
Low-Order Path Overhead Clock. 19.44 MHz clock supplied to external cir-
cuits that receive the low-order path overhead data.
H19
LOPOHDATAOUT
O
Low-Order Path Overhead Data. (Line and Path REI and RDI, O bits, V5,
J2, Z6/N2, and Z7/K4 byte).
A20
LOPOHVALIDOUT
O
Low-Order Path Overhead Data Output Valid. This signal is a mask, which
indicates the location of the overhead bytes in the LOPOHDATAOUT.
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