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參數(shù)資料
| 型號： | 4565B2 |
| 廠商： | LSI CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909 |
| 封裝： | PLASTIC, BGA-909 |
| 文件頁數(shù)： | 22/61頁 |
| 文件大?。?/td> | 1691K |
| 代理商： | 4565B2 |
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Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
29
P1, U9, T4, R4,
N2, P4, U5, R5,
M1, T5, M2,
R8, N4, U2, L2,
K1
DATA[15:0]
I/O
Data [15:0]. 16-bit data bus input for write operations and output for read opera-
tions. DATA[15] is the MSB, and DATA[0] is the LSB.
U4, R1
PAR[1:0]
I/O
Data Parity. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], and
PAR[0] is the parity for DATA[7:0]
T3
DTN
O
Data Transfer Acknowledge. The delay associated with DTN going low depends
on the 4565B Ultramapper Full Transport Retiming Device block being accessed. In
asynchronous mode, when ADSN or DSN is deasserted, it will drive the DTN signal
high. When inactive, CSN will drive DTN to be 3-stated. The microprocessor should
wait after DTN is deasserted, before starting the next operation.
U8
HP_INTN
O od High-Priority and Low-Priority Interrupt. Active-low. Each functional block con-
tains its individual low-priority interrupt. High-priority interrupts are generated by
TMUX, STS1LT, and E13 blocks. Each interrupt is individually maskable. Requires
an external 5 k
pull-up resistor.
W1
LP_INTN
Y1
APS_INTN
O od Automatic Protection Switch Interrupt. Active-low. See the TMUX and STS1LT
sections in the Register Description for specific interrupts. Each interrupt is individ-
ually maskable. Requires an external 5 k
pull-up resistor.
Table 2-22. Boundary Scan (IEEE 1149.1)
Pin
Symbol
Type
Name/Description
AN22
TCK
I
Test Clock. This signal provides timing for boundary-scan test operations.
AP23
TDI
I pu
Test Data In. Boundary-scan test data input signal, sampled on the rising
edge of TCK.
AN23
TMS
I pu
Test Mode Select. Controls boundary-scan test operations. TMS is sampled
on the rising edge of TCK.
AG26
TRST
I pu
Test Reset (Active-Low). This signal provides an asynchronous reset for
the boundary-scan TAP controller.
AJ21
TDO
O
Test Data Out. Boundary-scan test data output signal is updated on the fall-
ing edge of TCK. The TDO output will be high-impedance, except when
transmitting test data.
Table 2-21. Microprocessor Interface (continued)
Pin
Symbol
Type
Name/Description
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