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參數(shù)資料
| 型號： | 4565B2 |
| 廠商： | LSI CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909 |
| 封裝： | PLASTIC, BGA-909 |
| 文件頁數(shù)： | 14/61頁 |
| 文件大?。?/td> | 1691K |
| 代理商： | 4565B2 |
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Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
21
2.4 Pin Definitions
This section describes the function of each of the device pins. All LVDS input buffers have a built-in 100
terminating
resistor with a center tap pin available for an external capacitor connection. All unused LVDS inputs may be left
unconnected. Pin functionality is descriptive information. The actual functionality is dependent upon the device
configuration via the registers.
Table 2-4. TMUX Block, High-Speed Interface I/O
Pin
Symbol Type
Name/Description
AM2
RHSDP
LIN Receive High-Speed Data. 622/155 Mbits/s input data. This is also an input to internal clock
and data recovery (CDR). CDR may be bypassed in 155 Mbits/s mode. In 622 Mbits/s mode, the
internal CDR must be used.
AM3
RHSDN
AM1
RHSCP
LIN Receive High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if CDR is bypassed. Not
used in 622 Mbits/s mode.
AN1
RHSCN
AF8
CTAPRH
—
Center Tap RH. LVDS buffer terminator center tap for RHSDP/N and RHSCP/N. An optional
0.1 F capacitor, connected between CTAP pin and ground, will improve the common-mode re-
jection of the LVDS input buffers.
AG27 LOSEXT I pu External Loss-of-Signal Input. Active level is programmable by register
TMUX_LOSEXT_LEVEL. Defaults to active-low. This pin can be part of the high-priority interrupt
when active. Usually connected to optical transceiver to indicate loss of signal.
AM5
THSDP
LOUT Transmit High-Speed Data. 622/155 Mbits/s output data. The frame location in slave mode is
determined by THSSYNC and transmit high-speed control parameter register
(TMUX_TFRAMEOFFSETA). In master mode, the frame timing is arbitrary.
AM6
THSDN
AN2 THSCOP LOUT Transmit High-Speed Clock Output. 622/155 MHz transmit output clock associated with
THSDP/N.
AP2 THSCON
AL5
RESHI
—
Resistor. A 100
, 1% resistor is required between the RESHI and RESLO pins as a reference
for the LVDS input buffer termination.
AL6
RESLO
AK6
REF10*
I
Reference 1.0 V. External 1 V reference voltage pin (optional).
AJ6
REF14*
I
Reference 1.4 V. External 1.4 V reference voltage pin (optional).
* Optional: selected by MPU/top-level register UMPR_LVDS_REF_SEL. External reference voltage can be sourced from a low-impedance resistor
(less than 1 k
) divider circuit decoupled with a 0.1 F capacitor. Please refer to Table 4-7 LVDS Interface dc Characteristics on page 36 for addi-
tional information.
Table 2-5. TMUX Block, Protection Link I/O
Pin
Symbol
Type
Name/Description
AN6
RPSDP
LIN Receive Protection High-Speed Data. 622/155 Mbits/s protection input data. Also input
to internal protection CDR. CDR may be bypassed in 155 Mbits/s mode. In 622 Mbits/s
mode, the internal CDR must be used.
AP6
RPSDN
AM7
RPSCP
LIN Receive Protection High-Speed Clock. 155 MHz input clock for 155 Mbits/s data if pro-
tection CDR is bypassed. Not used in 622 Mbits/s mode.
AM8
RPSCN
AG10
CTAPRP
—
Center Tap RP. LVDS buffer terminator center tap for RPSDP/N and RPSCP/N. An op-
tional 0.1 F capacitor, connected between CTAP pin and ground, will improve the com-
mon-mode rejection of the LVDS input buffers.
AP9
TPSDP
LOUT Transmit Protection High-Speed Data. 622/155 Mbits/s protection output data.
AN9
TPSDN
AN8
TPSCP
LOUT Transmit Protection High-Speed Clock. 622/155 MHz transmit output clock associated
with TPSDP/N.
AP8
TPSCN
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