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參數(shù)資料
| 型號： | 29PL256N |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁模式閃存 |
| 文件頁數(shù)： | 71/74頁 |
| 文件大小： | 1968K |
| 代理商： | 29PL256N |
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June 6, 2007 S29PL-N_00_A5
S29PL-N MirrorBit
Flash Family
71
D a t a
S h e e t
( P r e l i m i n a r y )
Table 13.2
System Interface String
Addresses
Data
Description
1Bh
0027h
V
CC
Min. (write/erase)
D7 – D4: volt, D3 – D0: 100 millivolt
1Ch
0036h
V
CC
Max. (write/erase)
D7 – D4: volt, D3 – D0: 100 millivolt
1Dh
0000h
V
PP
Min. voltage (00h = no V
PP
pin present)
V
PP
Max. voltage (00h = no V
PP
pin present)
Typical timeout per single byte/word write 2
N
μs
1Eh
0000h
1Fh
0006h
20h
0009h
Typical timeout for Min. size buffer write 2
N
μs (00h = not supported)
21h
000Bh
Typical timeout per individual block erase 2
N
ms
22h
0000h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
0003h
Max. timeout for byte/word write 2
N
times typical
24h
0003h
Max. timeout for buffer write 2
N
times typical
25h
0002h
Max. timeout per individual block erase 2
N
times typical
26h
0000h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
Table 13.3
Device Geometry Definition
Addresses
Data
Description
27h
0019h (PL256N)
0018h (PL127N)
0018h (PL129N)
Device Size = 2
N
byte
28h
29h
0001h
0000h
Flash Device Interface description (see CFI publication 100)
2Ah
2Bh
0006h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0000h
0001h
Erase Block Region 1 Information
(see the CFI specification or CFI publication 100)
31h
007Dh (PL256N)
003Dh (PL127N)
003Dh (PL129N)
Erase Block Region 2 Information
(see the CFI specification or CFI publication 100)
32h
33h
34h
0000h
0000h
0004h
35h
36h
37h
38h
0003h
0000h
0000h
0001h
Erase Block Region 3 Information
(see the CFI specification or CFI publication 100)
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