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參數(shù)資料
| 型號： | 29PL256N |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁模式閃存 |
| 文件頁數(shù)： | 22/74頁 |
| 文件大?。?/td> | 1968K |
| 代理商： | 29PL256N |
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22
S29PL-N MirrorBit
Flash Family
S29PL-N_00_A5 June 6, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
7.2.2
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The random or
initial page access is t
ACC
or t
CE
and subsequent page read accesses (as long as the locations specified by
the microprocessor falls within that page) is equivalent to t
PACC
. When CE# is deasserted (= V
IH
), the
reassertion of CE# for subsequent access has access time of t
ACC
or t
CE
. Here again, CE# selects the device
and OE# is the output control and should be used to gate data to the output inputs if the device is selected.
Fast page mode accesses are obtained by keeping A
max
– A3 constant and changing A2 – A0 to select the
specific word within that page.
Address bits A
max
– A3 select an 8-word page, and address bits A2 – A0 select a specific word within that
page. This is an asynchronous operation with the microprocessor supplying the specific word location. See
Table 7.3
for details on selecting specific words.
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded
Erase algorithm. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All
data is latched on the rising edge of WE# or CE#, whichever happens first.
Reads from the memory array may be performed in conjunction with the Erase Suspend and Program
Suspend features. After the device accepts an Erase Suspend command, the corresponding bank enters the
erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector
within the same bank. The system can read array data using the standard read timing, except that if it reads
at an address within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the system may once again read array data with the
same exception. After the device accepts a Program Suspend command, the corresponding bank enters the
program-suspend-read mode, after which the system can read data from any non-program-suspended sector
within the same bank.
Table 7.3
Word Selection within a Page
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
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