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參數(shù)資料
| 型號(hào)： | 29PL256N |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁(yè)模式閃存 |
| 文件頁(yè)數(shù)： | 66/74頁(yè) |
| 文件大?。?/td> | 1968K |
| 代理商： | 29PL256N |
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66
S29PL-N MirrorBit
Flash Family
S29PL-N_00_A5 June 6, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
12. Appendix
This section contains information relating to software control or interfacing with the Flash device. For
additional information and assistance regarding software, see
Additional Resources
on page 17
, or explore
the Web at
www.spansion.com
.
Legend
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse whichever happens later.
PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first.
SA = Sector Address. PL127/129N = A22 – A15;
PL256N = A23 – A15.
BA = Bank Address. PL256N = A23 – A21; PL127N = A22 – A20; PL127N = A21 – A20.
WBL = Write Buffer Location. Address must be within the same write buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes
1. See
Table 7.1 on page 20
for description of bus operations.
2. All values are in hexadecimal.
3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the password verify
command, and any cycle reading at RD(0) and RD(1).
4. Data bits DQ15 – DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3 – PWD0.
5. Unless otherwise noted, these address bits are
don
’
t cares:
PL127: A22 – A15; 129N: A21 – A15; PL256N: A23 – A14.
6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset
command to return the device to reading array data.
7. No unlock or command cycles required when bank is reading array data.
Table 12.1
Memory Array Commands
Command Sequence
(Notes)
C
Bus Cycles (Notes
1
–
6
)
First
Second
Third
Fourth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (
7
)
1
RA
RD
Reset (
8
)
1
XXX
F0
Auto-
select
(
9
)
Manufacturer ID
4
555
AA
2AA
55
[BA]555
90
[BA]X00
0001
Device ID (
10
)
6
555
AA
2AA
55
[BA]555
90
[BA]X01
227E
[BA]X0E
(
10
)
[BA]X0F
2200
Indicator Bits
4
555
AA
2AA
55
[BA]555
90
[BA]X03
(
11
)
Program
4
555
AA
2AA
55
555
A0
PA
Data
Write to Buffer (
17
)
6
555
AA
2AA
55
SA
25
SA
WC
PA
PD
WBL
PD
Program Buffer to Flash
1
SA
29
Write to Buffer Abort Reset (
17
)
3
555
AA
2AA
55
555
F0
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (
14
)
1
BA
B0
Program/Erase Resume (
15
)
1
BA
30
CFI Query (
16
)
1
[BA]555
98
Unlock
Bypass
Mode
Unlock Bypass Entry
3
555
AA
2AA
55
555
20
Unlock Bypass Program (
12
,
13
)
2
XX
A0
PA
PD
Unlock Bypass Sector Erase (
12
,
13
)
2
XX
80
SA
30
Unlock Bypass Erase (
12
,
13
)
2
XX
80
XXX
10
Unlock Bypass CFI (
12
,
13
)
1
BA
98
Unlock Bypass Reset
2
XX
90
XXX
00
Secured Silicon Sector Command Definitions
Secured
Silicon
Sector
Secured Silicon Sector Entry (
18
)
3
555
AA
2AA
55
555
88
Secured Silicon Sector Program
2
XX
A0
PA
data
Secured Silicon Sector Read
1
RA
data
Secured Silicon Sector Exit (
19
)
4
555
AA
2AA
55
555
90
XX
00
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