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參數(shù)資料
| 型號： | 29PL256N |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁模式閃存 |
| 文件頁數(shù)： | 3/74頁 |
| 文件大?。?/td> | 1968K |
| 代理商： | 29PL256N |
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This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication Number
S29PL-N_00
Revision
A
Amendment
5
Issue Date
June 6, 2007
General Description
The Spansion Family Name is the latest generation 3.0-Volt page mode read family fabricated using the 110 nm Mirrorbit
TM
Flash process technology. These 8-word page-mode Flash devices are capable of performing simultaneous read and write
operations with zero latency on two separate banks. These devices offer fast page access times of 25 to 30 ns, with
corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to operate
without wait states. The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and CE2#) that allow
each half of the memory space to be controlled separately.
Distinctive Characteristics
Architectural Advantages
32-Word Write Buffer
Dual Chip Enable Inputs (only for S29PL129N)
– Two CE# inputs control selection of each half of the memory space
Single Power Supply Operation
– Full Voltage range of 2.7 – 3.6 V read, erase, and program
operations for battery-powered applications
– Voltage range of 2.7 – 3.1 V valid for PL-N MCP products
Simultaneous Read/Write Operation
– Data can be continuously read from one bank while executing
erase/program functions in another bank
– Zero latency switching from write to read operations
4-Bank Sector Architecture with Top and Bottom Boot Blocks
256-Word Secured Silicon Sector Region
– Up to 128 factory-locked words
– Up to 128 customer-lockable words
Manufactured on 0.11 μm Process Technology
Data Retention of 20 years Typical
Cycling Endurance of 100,000 Cycles per Sector Typical
Hardware Features
WP#/ACC (Write Protect/Acceleration) Input
– At V
IL
, hardware level protection for the first and last two 32 Kword
sectors.
– At V
IH
, allows the use of DYB/PPB sector protection
– At V
HH
, provides accelerated programming in a factory setting
Dual Boot and No Boot Options
Low V
CC
Write Inhibit
Security Features
Persistent Sector Protection
– A command sector protection method to lock combinations of
individual sectors to prevent program or erase operations within that
sector
– Sectors can be locked and unlocked in-system at V
CC
level
Password Sector Protection
– A sophisticated sector protection method locks combinations of
individual sectors to prevent program or erase operations within that
sector using a user defined 64-bit password
S29PL-N MirrorBit
Flash Family
29PL256N, S29PL127N, S29PL129N,
256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only
Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
(Preliminary)
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