參數(shù)資料
型號(hào)： 29PL256N
廠商： Spansion Inc.
英文描述： 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
中文描述： 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫(xiě)，頁(yè)模式閃存
文件頁(yè)數(shù)： 32/74頁(yè)
文件大小： 1968K
代理商： 29PL256N
32
S29PL-N MirrorBit
Flash Family
S29PL-N_00_A5 June 6, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
7.4.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by
Table 12.1 on page 66
. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these operations. The
Command Definition tables (
Table 12.1 on page 66
and
Table 12.2 on page 68
) show the address and data
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. See
Write Operation Status
on page 37
for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity.
Software Functions and Sample Code
The following is a C source code example of using the chip erase function. Refer to the
Spansion Low Level
Driver User’s Guide
(available on
www.spansion.com
) for general information on Spansion Flash memory
software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended */
*((UINT16 *)base_addr + 0x555) = 0x00AA; /* write unlock cycle 1 */
*((UINT16 *)base_addr + 0x2AA) = 0x0055; /* write unlock cycle 2 */
*((UINT16 *)base_addr + 0x555) = 0x0080; /* write setup command */
*((UINT16 *)base_addr + 0x555) = 0x00AA; /* write additional unlock cycle 1 */
*((UINT16 *)base_addr + 0x2AA) = 0x0055; /* write additional unlock cycle 2 */
*((UINT16 *)base_addr + 0x000) = 0x0010; /* write chip erase command */
Table 7.10
Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle
Description
Operation
Word Address
Data
1
Unlock
Write
Base + 555h
00AAh
2
Unlock
Write
Base + 2AAh
0055h
3
Setup Command
Write
Base + 555h
0080h
4
Unlock
Write
Base + 555h
00AAh
5
Unlock
Write
Base + 2AAh
0055h
6
Chip Erase Command
Write
Base + 555h
0010h
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