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參數(shù)資料
| 型號： | 29PL256N |
| 廠商： | Spansion Inc. |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 256/128/128字節(jié)（16/8/8 M中的x 16位），3.0伏的CMOS只同步讀/寫，頁模式閃存 |
| 文件頁數(shù)： | 61/74頁 |
| 文件大?。?/td> | 1968K |
| 代理商： | 29PL256N |
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June 6, 2007 S29PL-N_00_A5
S29PL-N MirrorBit
Flash Family
61
D a t a
S h e e t
( P r e l i m i n a r y )
11.8.4
Erase/Program Timing
Notes
1. Not 100% tested.
2. In program operation timing, addresses are latched on the falling edge of WE#.
3. See
Program/Erase Operations on page 25
for more information.
4. Does not include the preprogramming time.
Parameter
Description (Notes)
Speed Options
Unit
JEDEC
Std
65
70
80
t
AVAV
t
WC
Write Cycle Time (
1
)
Min
65
70
80
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
35
ns
t
AHT
Address Hold Time From CE# or OE# high during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
30
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
10
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
40
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
25
ns
t
SR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation
Typ
40
μs
t
WHWH1
t
WHWH1
Accelerated Programming Operation
Typ
24
μs
t
WHWH2
t
WHWH2
Sector Erase Operation
Typ
1.6
sec
t
VHH
V
HH
Rise and Fall Times
Min
250
ns
t
RB
Write Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
t
WEP
Noise Pulse Margin on WE#
Max
3
ns
t
SEA
Sector Erase Accept Time-out
Max
50
μs
t
ESL
Erase Suspend Latency
Max
20
μs
t
PSL
Program Suspend Latency
Max
20
μs
t
ASP
Toggle Time During Sector Protection
Typ
100
μs
t
PSP
Toggle Time During Programming Within a Protected Sector
Typ
1
μs
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