參數(shù)資料
型號： 29LV160BE
廠商： Fujitsu Limited
英文描述： 16M (2M X 8/1M X 16) BIT
中文描述： 16米（2米x 8/1M × 16）位
文件頁數(shù)： 25/59頁
文件大小： 653K
代理商： 29LV160BE
MBM29LV160TE/BE
-70/90/12
25
RESET
Hardware Reset Pin
The MBM29LV160TE/BE device may be reset by driving the RESET pin to V
IL
. The RESET pin has a pulse
requirement and has to be kept low (V
IL
) for at least “t
RP
” in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode “t
READY
” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
device requires an additional “t
RH
” before it allows read access. When the RESET pin is low, the device will be
in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 13 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will
need to be erased again before they can be programmed.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160TE/BE device. When
this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ
0
to DQ
15
. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ
15
/A
-1
pin
becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and DQ
8
to DQ
15
bits are ignored. Refer to
Figures 14, 15 and 16 for the timing diagram.
Data Protection
The MBM29LV160TE/BE is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequence.
The device also incorporates several features to prevent inadvertent write cycles resulting form V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(min.). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above V
LKO
(min.).
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be
erased again prior to programming.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write, CE and WE must
be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
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