參數(shù)資料
型號(hào): 28F640J5
廠商: Intel Corp.
英文描述: 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器)
中文描述: 5伏特英特爾StrataFlash存儲(chǔ)器(5V的6400位英特爾的StrataFlash閃速存儲(chǔ)器)
文件頁(yè)數(shù): 49/53頁(yè)
文件大小: 272K
代理商: 28F640J5
E
28F320J5/28F640J5
49
PRELIMINARY
A
IN
A
IN
A
B
C
D
E
F
W15
D
IN
W11
W10
Valid
SRD
D
IN
D
IN
W13
W14
W7
W3
W4
High Z
W2
W9
W16
W12
W6
W1
W5
W8
V
IH
V
IL
ADDRESSES [A]
Disabled (V
IH
)
Enabled (V
IL
)
CE
X
, (WE#) [E(W)]
V
IH
V
IL
OE# [G]
Disabled (V
IH
)
Enabled (V
IL
)
WE#, (CE
) [W(E)]
V
IH
V
IL
DATA [D/Q]
V
OH
V
OL
V
HH
STS [R]
V
IH
V
IL
RP# [P]
V
PENLK
V
IL
V
PEN
[V]
V
PENH
0606_17
NOTES:
CE
X
low is defined as the first edge of CE
0
, CE
1
, or CE
2
that enables the device. CE
X
high is defined at the first edge of CE
0
,
CE
1
, or CE
2
that disables the device (see Table 2, Chip Enable Truth Table.
STS is shown in its default mode (RY/BY#).
A.
V
CC
power-up and standby.
B.
Write block erase, write buffer, or program setup.
C.
Write block erase or write buffer confirm, or valid address and data.
D.
Automated erase delay.
E.
Read status register or query data.
F.
Write Read Array command.
Figure 17. AC Waveform for Write Operations
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