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參數(shù)資料
| 型號： | 28F640J5 |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲器) |
| 中文描述： | 5伏特英特爾StrataFlash存儲器（5V的6400位英特爾的StrataFlash閃速存儲器） |
| 文件頁數(shù)： | 34/53頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 28F640J5 |
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28F320J5/28F640J5
E
34
PRELIMINARY
Start
Write Word or Byte
Count, Block Address
Write Buffer Data,
Start Address
X = 0
X = X + 1
Write Next Buffer Data,
Device Address
Abort Write to
Buffer Command
Check
X = N
Another Write to
Buffer
Read Status Register
SR.7 =
Programming
Complete
Read Extended
Status Register
XSR.7 =
1
No
Yes
No
No
1
Write to Buffer
Aborted
Yes
No
Yes
Full Status
Check if Desired
Program Buffer to Flash
Confirm D0H
Issue Write to Buffer
Command E8H, Block
Address
Write to Another
Block Address
Write to
Buffer Time-Out
0
Set Time-Out
Issue Read
Status Command
Yes
Bus
Operation
Command
Comments
Write
Write to Buffer
Data = E8H
Block Address
Read
XSR. 7 = Valid
Addr = Block Address
Standby
Check XSR. 7
1 = Write Buffer Available
0 = Write Buffer Not Available
Write
(Note 1, 2)
Data = N = Word/Byte Count
N = 0 Corresponds to Count = 1
Addr = Block Address
Write
(Note 3, 4)
Data = Write Buffer Data
Addr = Device Start Address
Write
(Note 5, 6)
Data = Write Buffer Data
Addr = Device Address
Write
Program Buffer
to Flash
Confirm
Data = D0H
Addr = Block Address
Read
(Note 7)
Status Register Data with the
Device Enabled, OE# Low
Updates SR
Addr = Block Address
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
1. Byte or word count values on DQ
- DQ
are loaded into the
count register. Count ranges on this device for byte mode are N
= 00H to 1FH and for word mode are N = 0000H to 000FH.
2. The device now outputs the status register when read (XSR is
no longer available).
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A
4
- A
0
of the start
address = 0).
5. The device aborts the Write to Buffer command if the current
address is outside of the original block address.
6. The status register indicates an "improper command
sequence" if the Write to Buffer command is aborted. Follow this
with a Clear Status Register command.
7. Toggling OE# (low to high to low) updates the status register.
This can be done in place of issuing the Read Status Register
command.
Full status check can be done after all erase and write sequences
complete. Write FFH after the last operation to reset the device to
read array mode.
0
1
0606_07
Figure 7. Write to Buffer Flowchart
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| 28F640L30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
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