參數(shù)資料
型號(hào)： 28F640J5
廠商： Intel Corp.
英文描述： 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器)
中文描述： 5伏特英特爾StrataFlash存儲(chǔ)器（5V的6400位英特爾的StrataFlash閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 27/53頁(yè)
文件大?。?/td> 272K
代理商： 28F640J5
E
the STS pin or status register bit SR.7. Toggle OE#,
CE
0
, CE
1
, or CE
2
to update the status register.
28F320J5/28F640J5
27
PRELIMINARY
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to
“1.” Also,
reliable block erasure can only occur when
V
CC
is valid and V
PEN
= V
PENH
. If block erase is
attempted while V
PEN
≤
V
PENLK
, SR.3 and SR.5 will
be set to “1.” Successful block erase requires that
the corresponding block lock-bit be cleared or, if
set, that RP# = V
HH
. If block erase is attempted
when the corresponding block lock-bit is set and
RP# = V
IH
, SR.1 and SR.5 will be set to “1.” Block
erase operations with V
IH
< RP# < V
HH
produce
spurious results and should not be attempted.
4.7
Block Erase Suspend
Command
The Block Erase Suspend command allows
block-erase interruption to read or program data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bit SR.7
then SR.6 can determine when the block erase
operation has been suspended (both will be set to
“1”). In default mode, STS will also transition to
V
OH
. Specification t
WHRH
defines the block erase
suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A program command sequence can
also be issued during erase suspend to program
data in other blocks. During a program operation
with block erase suspended, status register bit
SR.7 will return to “0” and the STS output (in default
mode) will transition to V
OL
.
The only other valid commands while block erase is
suspended are Read Query, Read Status Register,
Clear Status Register, Configure, and Block Erase
Resume. After a Block Erase Resume command is
written to the flash memory, the WSM will continue
the block erase process. Status register bits SR.6
and SR.7 will automatically clear and STS (in
default mode) will return to V
OL
. After the Erase
Resume
command
is
automatically outputs status register data when
read (see Figure 10). V
PEN
must remain at V
PENH
(the same V
PEN
level used for block erase) while
block erase is suspended. RP# must also remain at
V
IH
or V
HH
(the same RP# level used for block
erase). Block erase cannot resume until program
operations initiated during block erase suspend
have completed.
written,
the
device
4.8
Write to Buffer Command
To program the flash device, a Write to Buffer
command sequence is initiated. A variable number
of bytes, up to the buffer size, can be loaded into
the buffer and written to the flash device. First, the
Write to Buffer setup command is issued along with
the Block Address (see Figure 7,
Write to Buffer
Flowchart
). At this point, the eXtended Status
Register (XSR, see Table 17) information is loaded
and XSR.7 reverts to “buffer available” status. If
XSR.7 = 0, the write buffer is not available. To retry,
continue monitoring XSR.7 by issuing the Write to
Buffer setup command with the Block Address until
XSR.7 = 1. When XSR.7 transitions to a “1,” the
buffer is ready for loading.
Now a word/byte count is given to the part with the
Block Address. On the next write, a device start
address is given along with the write buffer data.
Subsequent writes provide additional device
addresses and data, depending on the count. All
subsequent addresses must lie within the start
address plus the count.
Internally, this device programs many flash cells in
parallel. Because of this parallel programming,
maximum programming performance and lower
power are obtained by aligning the start address at
the
beginning
of
a
(i.e., A
4
–A
0
of the start address = 0).
write
buffer
boundary
After the final buffer data is given, a Write Confirm
command is issued. This initiates the WSM (Write
State Machine) to begin copying the buffer data to
the flash array. If a command other than Write
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