參數(shù)資料
型號: 28F640J5
廠商: Intel Corp.
英文描述: 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲器)
中文描述: 5伏特英特爾StrataFlash存儲器(5V的6400位英特爾的StrataFlash閃速存儲器)
文件頁數(shù): 30/53頁
文件大小: 272K
代理商: 28F640J5
28F320J5/28F640J5
E
30
PRELIMINARY
successful clear block lock-bits operation requires
that the master lock-bit is not set or, if the master
lock-bit is set, that RP# = V
HH
. If it is attempted with
the master lock-bit set and RP# = V
IH
, SR.1 and
SR.5 will be set to
“1” and the operation will fail. A
clear block lock-bits operation with V
IH
< RP# < V
HH
produce spurious results and should not be
attempted.
If a clear block lock-bits operation is aborted due to
V
PEN
or V
CC
transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-
bits is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
Table 14. Write Protection Alternatives
Operation
Block Erase or
Program
Master
Lock-Bit
Block
Lock-Bit
0
1
RP#
Effect
V
IH
or V
HH
Block Erase and Program Enabled
V
IH
Block is Locked. Block Erase and Program Disabled
V
HH
Block Lock-Bit Override. Block Erase and Program
Enabled
V
IH
or V
HH
Set or Clear Block Lock-Bit Enabled
V
IH
Master Lock-Bit Is Set. Set or Clear Block Lock-Bit
Disabled
V
HH
Master Lock-Bit Override. Set or Clear Block Lock-Bit
Enabled
V
IH
Set Master Lock-Bit Disabled
V
HH
Set Master Lock-Bit Enabled
X
Set or Clear Block
Lock-Bit
0
1
X
X
Set Master
Lock-Bit
X
X
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