- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371435 > 28F640J5 (Intel Corp.) 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | 28F640J5 |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器) |
| 中文描述： | 5伏特英特爾StrataFlash存儲(chǔ)器（5V的6400位英特爾的StrataFlash閃速存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 38/53頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | 28F640J5 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)當(dāng)前第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)
28F320J5/28F640J5
E
38
PRELIMINARY
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Write
Write
Standby
Repeat for subsequent lock-bit operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations
Write FFH after the last lock-bit set operation to place device in read
array mode.
Bus
Operation
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command, in cases where multiple lock-bits are set before full
status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
1
0
Standby
Command
Set Block/Master
Lock-Bit Setup
Set Block or Master
Lock-Bit Confirm
Comments
Data = 60H
Addr =Block Address (Block),
Device Address (Master)
Data = 01H (Block)
F1H (Master)
Addr = Block Address (Block),
Device Address (Master)
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.1
1 = Device Protect RP# = V
(Set Master Lock-Bit Operation)
RP# = V
, Master Lock-Bit Is Set
(set Block Lock-Bit Operation)
Read Status Register
Data (See Above)
Voltage Range Error
Device Protect Error
SR.3 =
SR. 1 =
1
0
1
0
Command Sequence
Error
SR.4,5 =
1
0
Set Lock-Bit Error
SR.4 =
1
0
Read
Status Register Data
Standby
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Check SR.4
1 = Set Lock-Bit Error
Set Lock-Bit
Successful
0606_11
Figure 11. Set Block Lock-Bit Flowchart
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F400B3 | SMART 3 ADVANCED BOOT BLOCK WORD-WIDE |
| 28F400BL-TB | 4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BV-TB | 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BX-TB | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 28F410-100M1 | 4M-BIT (512K X 8) CMOS FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| 28F640L30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。