參數(shù)資料
型號： 28F200B5
廠商： Intel Corp.
英文描述： 5V Boot Block Flash Memory(5 V 引導(dǎo)塊閃速存儲器)
中文描述： 5V的啟動塊閃存（5伏引導(dǎo)塊閃速存儲器）
文件頁數(shù)： 7/44頁
文件大小： 345K
代理商： 28F200B5
E
28F200B5, 28F004/400B5, 28F800B5
7
PRELIMINARY
Table 2. Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
18
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally latched
during a write cycle.
28F200: A[0
–16], 28F400: A[0–17], 28F800: A[0–18], 28F004: A[0–18]
ADDRESS INPUT:
When A
9
is at V
HH
the signature mode is accessed. During
this mode, A
0
decodes between the manufacturer and device IDs. When BYTE#
is at a logic low, only the lower byte of the signatures are read. DQ
15
/A
–1
is a
don’t care in the signature mode when BYTE# is low.
A
9
INPUT
DQ
0
–DQ
7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, intelligent identifier and status register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
DQ
8
–DQ
15
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ
15
/A
–1
becomes the lowest order address for data output on DQ
0
–DQ
7
.
Not applicable to 28F004B5.
CE#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data buffers during
a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the command register and array blocks. WE#
is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses three voltage levels (V
IL
, V
IH
, and V
HH
) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep power-down mode
,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation
. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at V
HH
, the boot block is unlocked
and can be programmed or
erased. This overrides any control from the WP# input.
相關(guān)PDF資料
PDF描述
28F200BV-TB 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F200BX 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
28F200BX-TB 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
28F200BX-B 5V or Adjustable, Low-Voltage, Step-Up DC-DC Controller
28F200BX-T Evaluation Kit for the MAX608
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F200BL-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
28F200BL-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
28F200BL-T/B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
28F200BL-TB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
28F200BV-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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