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參數(shù)資料
| 型號： | 28F200B5 |
| 廠商： | Intel Corp. |
| 英文描述： | 5V Boot Block Flash Memory(5 V 引導塊閃速存儲器) |
| 中文描述： | 5V的啟動塊閃存（5伏引導塊閃速存儲器） |
| 文件頁數(shù)： | 19/44頁 |
| 文件大?。?/td> | 345K |
| 代理商： | 28F200B5 |
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E
28F200B5, 28F004/400B5, 28F800B5
19
PRELIMINARY
Table 6. Command Codes and Descriptions
(Continued)
Code
Device Mode
Description
50
Clear Status
Register
The WSM can only set the program status and erase status bits in the status
register to
“1”; it cannot clear them to “0.”
The status register operates in this fashion for two reasons. The first is to give the
host CPU the flexibility to read the status bits at any time. Second, when
programming a string of bytes, a single status register query after programming the
string may be more efficient, since it will return the accumulated error status of the
entire string. See Section 3.2.3.1.
90
Intelligent
Identifier
Puts the device into the intelligent identifier read mode, so that reading the device
will output the manufacturer and device codes. (A
0
= 0 for manufacturer,
A
0
= 1 for device, all other address inputs are ignored). See Section 3.2.2.
Table 7. Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Command
Note
Oper
Addr
Data
Oper
Addr
Data
Read Array
Write
X
FFH
Intelligent Identifier
2,4
Write
X
90H
Read
IA
IID
Read Status Register
3
Write
X
70H
Read
X
SRD
Clear Status Register
3
Write
X
50H
Word/Byte Program
6,7
Write
PA
40H/10H
Write
PA
PD
Block Erase/Confirm
5
Write
BA
20H
Write
BA
D0H
Erase Suspend
Write
X
B0H
Erase Resume
Write
X
D0H
ADDRESS
BA = Block Address
IA = Identifier Address
PA = Program Address
X = Don’t Care
DATA
SRD = Status Register Data
IID = Identifier Data
PD = Program Data
NOTES:
1.
Bus operations are defined in Tables 3 and 4.
2.
IA = Identifier Address: A
0
= 0 for manufacturer code, A
0
= 1 for device code.
3.
SRD - Data read from Status Register.
4.
IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and
device codes.
5.
BA = Address within the block being erased.
6.
PA = Address to be programmed. PD = Data to be programmed at location PA.
7.
Either 40H or 10H commands is valid.
8.
When writing commands to the device, the upper data bus [DQ
8
–DQ
15
] = X which is either V
IL
or V
IH
, to minimize current
draw.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 28F200BL-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F200BL-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K x 16. 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F200BL-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| 28F200BL-TB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F200BV-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
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