參數(shù)資料
型號(hào): 28F200B5
廠商: Intel Corp.
英文描述: 5V Boot Block Flash Memory(5 V 引導(dǎo)塊閃速存儲(chǔ)器)
中文描述: 5V的啟動(dòng)塊閃存(5伏引導(dǎo)塊閃速存儲(chǔ)器)
文件頁(yè)數(shù): 33/44頁(yè)
文件大小: 345K
代理商: 28F200B5
E
28F200B5, 28F004/400B5, 28F800B5
33
PRELIMINARY
C
L
OUT
V
CC
DEVICE
UNDER
TEST
R
1
R
2
0599-12
NOTE:
C
L
includes jig capacitance.
Figure 13. Test Configuration
Test Configuration Component Values
Test Configuration
C
L
(pF)
R
1
(
) R
2
(
)
5 V Standard Test
100
580
390
5 V High-Speed Test
30
580
390
IH
V
IL
V
RP# (P)
PLPH
t
IH
V
IL
V
RP# (P)
PLPH
t
(A) Reset during Read Mode
Abort
Complete
PLRH
PHQV
PHWL
PHEL
t
t
t
PHQV
PHWL
PHEL
t
t
t
(B) Reset during Program or Block Erase, <
PLPH
PLRH
t
t
IH
V
IL
V
RP# (P)
PLPH
t
Abort
Complete
PHQV
PHWL
PHEL
t
t
t
PLRH
t
Deep
Power-
Down
(C) Reset Program or Block Erase, >
PLPH
PLRH
t
0599-13
Figure 14. AC Waveform for Reset Operation
Table 10. Reset Specifications
(1)
Sym
Parameter
Min
Max
Unit
t
PLPH
RP# Pulse Low
Time
60
ns
t
PLRH
RP# Low to Reset
during Prog/Erase
12
μ
s
1.
2.
If RP# is tied to V
CC
, these specs are not applicable.
These specifications are valid for all product versions
(packages and speeds).
If RP# is asserted while a program or block erase, is
not executing, the reset will complete within t
PLPH
.
A reset time, t
, is required after t
until outputs
are valid. See Section 3.1.5 for detailed information.
3.
4.
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