參數(shù)資料
型號(hào): 28F200B5
廠商: Intel Corp.
英文描述: 5V Boot Block Flash Memory(5 V 引導(dǎo)塊閃速存儲(chǔ)器)
中文描述: 5V的啟動(dòng)塊閃存(5伏引導(dǎo)塊閃速存儲(chǔ)器)
文件頁(yè)數(shù): 35/44頁(yè)
文件大小: 345K
代理商: 28F200B5
E
5.7
28F200B5, 28F004/400B5, 28F800B5
35
PRELIMINARY
AC Characteristics
—Read Operations—Automotive Temperature
Speed
–80
–90
#
Sym
Parameter
Density
V
CC
5 V
±
10%
(5)
5 V
±
10%
(5)
Unit
Load
100 pF
100 pF
Notes
Min
Max
Min
Max
R1
t
AVAV
Read Cycle Time
2, 4 Mbit
80
n/a
ns
8 Mbit
80
90
ns
R2
t
AVQV
Address to Output Delay
2, 4 Mbit
80
n/a
ns
8 Mbit
80
90
ns
R3
t
ELQV
CE# to Output Delay
2, 4 Mbit
2
80
n/a
ns
8 Mbit
80
90
ns
R4
t
GLQV
OE# to Output Delay
2
40
40
ns
R5
t
PHQV
RP# to Output Delay
550
550
ns
R6
t
ELQX
CE# to Output in Low Z
3
0
0
ns
R7
t
GLQX
OE# to Output in Low Z
3
0
0
ns
R8
t
EHQZ
CE# to Output in High Z
3
25
25
ns
R9
t
GHQZ
OE# to Output in High Z
3
25
25
ns
R10
t
OH
Output Hold from Address, CE#, or OE#
Change, Whichever Occurs First
3
0
0
ns
NOTES:
1.
2.
3.
4.
5.
6.
See AC Input/Output Reference Waveform for timing measurements.
OE# may be delayed up to t
CE
–t
OE
after the falling edge of CE# without impact on t
CE
.
Sampled, but not 100% tested.
See
Test Configuration
(Figure 13), 5 V High-Speed Test component values.
See
Test Configuration
(Figure 13), 5 V Standard Test component values.
Dynamic BYTE# switching between word and byte modes is not supported. Mode changes must be made when the device
is in deep power-down or powered down.
As of the publication date of this document, not all 28F200B5 –60 devices meet the 55 ns read specification. Please refer
to the
5 Volt Boot Block Flash Memory Family 28F200B5, 28F004/400B5, 28F800B5 Specification Update
to determine
the specific 28F200B5 –T/B60 material that is capable of 55 ns read access times. All other 28F200B5 T/B60 devices are
capable of 60 ns read access times when V
CC
= 5 V ± 5% and 30 pF load.
7.
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