參數(shù)資料
型號(hào)： 28F020
廠商： Intel Corp.
英文描述： 5 V Bulk Erase Flash Memory(5V 整體擦寫(xiě)閃速存儲(chǔ)器)
中文描述： 5伏體擦除閃存（5V的整體擦寫(xiě)閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 9/47頁(yè)
文件大小： 758K
代理商： 28F020
E
28F010/28F020
9
28F020
28F020
A
0
-A
17
DQ
0
-DQ
7
CE
#
WE
#
OE
#
A
0
-A
17
DQ
0
-DQ
7
CE
#
BHE
#
OE
#
V
CC
V
CC
V
PP
V
PP
80C186
System Bus
A
1
-A
18
DQ
8
-DQ
15
Address Decoded
Chip Select
DQ
0
-DQ
7
WE
#
WR
#
RD
#
V
CC
V
CC
A
0
290207-4
Figure 3. 28F020 in a 80C186 System
2.0
PRINCIPLES OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
5 Volt Bulk Erase introduces a command register to
manage this new functionality. The command
register allows for: 100% TTL-level control inputs;
fixed
power
supplies
programming; and maximum EPROM compatibility.
during
erasure
and
In the absence of high voltage on the V
PP
pin, the
5 Volt Bulk Erase is a read-only memory.
Manipulation of the external memory control pins
yields the standard EPROM read, standby, output
disable, and intelligent identifier operations.
The same EPROM read, standby, and output
disable operations are available when high voltage
is applied to the V
PP
pin. In addition, high voltage
on V
PP
enables erasure and programming of the
device. All functions associated with altering
memory
contents
—intelligent
erase verify, program, and program verify—are
accessed via the command register.
identifier,
erase,
Commands are written to the register using
standard microprocessor write timings. Register
contents serve as input to an internal state machine
which controls the erase and programming circuitry.
Write cycles also internally latch addresses and
data needed for programming or erase operations.
With the appropriate command written to the
register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output data for erase and program
verification.
2.1
Integrated Stop Timer
Successive command write cycles define the
durations of program and erase operations;
specifically, the program or erase time durations are
normally terminated by associated Program or
Erase Verify commands. An integrated stop timer
provides simplified timing control over these
operations; thus eliminating the need for maximum
program/erase timing specifications. Programming
and erase pulse durations are minimums only.
When the stop timer terminates a program or erase
operation, the device enters an inactive state and
remains inactive until receiving the appropriate
Verify or Reset command.
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