參數(shù)資料
型號： 28222-14
廠商： Conexant Systems, Inc.
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： 自動柜員機發(fā)射機/接收機的UTOPIA接口
文件頁數(shù)： 89/161頁
文件大小： 1832K
代理商： 28222-14
CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.2 Control Register Overview
100046C
Conexant
3-3
Receive Idle Header Mask - Octets 3, 4
0x16
HDR_VAL0_34
Receive Port 0 Header Value - Octets 3, 4
0x17
HDR_VAL1_12
Receive Port 1 Header Value - Octets 1, 2
0x18
HDR_VAL1_34
Receive Port 1 Header Value - Octets 3, 4
0x19
HDR_VAL2_12
Receive Port 2 Header Value - Octets 1, 2
0x1A
HDR_VAL2_34
Receive Port 2 Header Value - Octets 3, 4
0x1B
HDR_VAL3_12
Receive Port 3 Header Value - Octets 1, 2
0x1C
HDR_VAL3_34
Receive Port 3 Header Value - Octets 3, 4
0x1D
HDR_MSK0_12
Receive Port 0 Header Mask - Octets 1, 2
0x1E
HDR_MSK0_34
Receive Port 0 Header Mask - Octets 3, 4
0x1F
HDR_MSK1_12
Receive Port 1 Header Mask - Octets 1, 2
0x20
HDR_MSK1_34
Receive Port 1 Header Mask - Octets 3, 4
0x21
HDR_MSK2_12
Receive Port 2 Header Mask - Octets 1, 2
0x22
HDR_MSK2_34
Receive Port 2 Header Mask - Octets 3, 4
0x23
HDR_MSK3_12
Receive Port 3 Header Mask - Octets 1, 2
0x24
HDR_MSK3_34
Receive Port 3 Header Mask - Octets 3, 4
0x25
RX_IDLE_12
Receive Idle Header Value - Octets 1, 2
0x26
RX_IDLE_34
Receive Idle Header Value - Octets 3, 4
0x27
IDLE_MSK_12
Receive Idle Header Mask - Octets 1, 2
0x28
IDLE_MSK_34
0x29
CONFIG_4
Configuration Control Register 4
0x2A
IDLE_PAY
Transmit Idle Cell Payload Value
0x2B
UTOPIA_1
Utopia Port Control Register 1
0x2C
UTOPIA_2
Utopia Port Control Register 2
0x2D
EN_LINE_INT
Line/PHY Status Interrupt Enable Register
0x2E
EN_EVENT_INT
Status Event Interrupt Enable Register
0x2F
EN_OVFL_INT
Counter Overflow Interrupt Enable Register
0x30
EN_CELL_INT
Cell Counter Interrupt Enable Register
0x31
CONFIG_5
Configuration Control Register 5
0x32
TX_K1K2
Transmit K1, K2 Value for SONET APS
0x33
RX_K1K2
Receive K1, K2 Value for SONET APS
0x60
DL_CTRL_STAT
HDLC Data Link Control and Status Register
Table 3-2. ATM Transmitter/Receiver Microprocessor Control Registers (2 of 2)
Address
Name
Function
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