參數(shù)資料
型號： 28222-14
廠商： Conexant Systems, Inc.
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： 自動柜員機發(fā)射機/接收機的UTOPIA接口
文件頁數(shù)： 33/161頁
文件大?。?/td> 1832K
代理商： 28222-14
CN8223
1.0 Product Description
ATM Transmitter/Receiver with UTOPIA Interface
1.10 Pin Definitions
100046C
Conexant
1-23
M
SEL8BIT
8/16 Bit Mode
Select
37
CMOS/TTL
I
If asserted, this pin selects an 8-bit
microprocessor bus. If not asserted, it selects a
16-bit bus.
PRCLK
Processor Clock
97
CMOS/TTL
I
Clock input to the microprocessor interface. All
inputs are synchronous to this clock except OE~.
All read and write operations require two cycles
of PRCLK. PRCLK must run continuously at a
minimum frequency of 2 times the cell rate.
CS~
Chip Select
96
CMOS/TTL
I
Must be logic low to address chip. Must be low
to enable a read or write operation and should
be stable throughout the cycle.
AS~
Address Strobe
94
CMOS/TTL
I
If this pin is low, a new address is loaded on the
rising edge of PRCLK for the operation in the
following clock period. If this pin is high and
CS~ is low, a read or a write operation is
executed. The address strobe can stay low for
multiple clock periods. Address strobe cannot
stay high with CS~ low for multiple clock
periods.
W/R~
Write/Read Control
95
CMOS/TTL
I
If this pin is low when CS~ is low, the following
cycle is a read operation. If this signal is high
when CS~ is low, the data presented at the end
of the following clock cycle will be written if CS~
is still low on that cycle.
OE~
Output Enable
92
CMOS/TTL
I
This signal must be low to enable the data
output for a read cycle. Data bus outputs are
three-stated if this signal is high. The data is
valid between clock edges on a read cycle when
this pin is low. This pin may be connected
directly to ground, if desired.
DL_INT
FEAC/HDLC
Interrupt
63
CMOS/TTL
O
Active-low data link channel interrupt output
with open drain.
STAT_INT
Status/Counter
Interrupt
64
CMOS/TTL
O
Active-low status/counter interrupt with open
drain.
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
Processor Data
Bus
65
68
69
70
71
72
73
74
75
76
77
78
79
82
83
84
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
This signal is a 16-bit bidirectional data bus for
read and write data.
Table 1-2. Hardware Signal Definitions (4 of 5)
Pin Label
Signal Name
No.
Type
I/O
Definition
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