參數(shù)資料
型號(hào)： 28222-14
廠商： Conexant Systems, Inc.
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： 自動(dòng)柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口
文件頁數(shù)： 124/161頁
文件大?。?/td> 1832K
代理商： 28222-14
3.0 Registers
CN8223
3.7 Status Register Overview
ATM Transmitter/Receiver with UTOPIA Interface
3-38
Conexant
100046C
Set when a cell is transmitted from port 0.
0x3B
—
CELL_STATUS (Interrupt Status Register)
The CELL_STATUS register is located at address 0x3B.
0x3C
—
RXFEAC_VER (Receive FEAC/Part Number/Version Number Register)
The RXFEAC_VER register is located at address 0x3C. The lower 8 bits have fixed values. Programming of the
FEAC channel and use of these interrupts is discussed in
Section 2.8
.
Bit
Field
Size
Name
Description
15
1
Cell Sent Cntr Ovfl
–
Port 3
Set if the CELL_SENT_CNT3 counter overflows.
14
1
Cell Sent Cntr Ovfl
–
Port 2
Set if the CELL_SENT_CNT2 counter overflows.
13
1
Cell Sent Cntr Ovfl
–
Port 1
Set if the CELL_SENT_CNT1 counter overflows.
12
1
Cell Sent Cntr Ovfl
–
Port 0
Set if the CELL_SENT_CNT0 counter overflows.
11
1
Cell Rcvd Cntr Ovfl-Port 3
Set if the CELL_RCV_CNT3 counter overflows.
10
1
Cell Rcvd Cntr Ovfl-Port 2
Set if the CELL_RCV_CNT2 counter overflows.
9
1
Cell Rcvd Cntr Ovfl-Port 1
Set if the CELL_RCV_CNT1 counter overflows.
8
1
Cell Rcvd Cntr Ovfl-Port 0
Set if the CELL_RCV_CNT0 counter overflows.
7
1
Cell Rcvd
–
Port 3
Enables port 3 header match interrupt.
6
1
Cell Rcvd
–
Port 2
Enables port 2 header match interrupt.
5
1
Cell Rcvd
–
Port 1
Enables port 1 header match interrupt.
4
1
Cell Rcvd
–
Port 0
Enables port 0 header match interrupt.
3
1
Cell Sent
–
Port 3
Set when a cell is transmitted from port 3.
2
1
Cell Sent
–
Port 2
Set when a cell is transmitted from port 2.
1
1
Cell Sent
–
Port 1
Set when a cell is transmitted from port 1.
0
1
Cell Sent
–
Port 0
Bit
Field
Size
Name
Description
15
–
10
6
Receive FEAC Data
Contains the data received by the FEAC receiver.
9
1
Receive FEAC
Interrupt
Indicates that the interrupt on the DL_INT pin was from the FEAC receiver when the
internal DS3 framer is enabled.
8
1
Transmit FEAC
Interrupt
Indicates that the interrupt on the DL_INT pin was from the FEAC transmitter when
the internal DS3 framer is enabled.
7
–
4
4
Part Number
Fixed value is E (1110).
3
–
0
4
Version Number
Provides the version number of the part. CN8223 = 1 (0001)
相關(guān)PDF資料
PDF描述
28233-11 ATM Transmitter/Receiver with UTOPIA Interface
28C010TRPDB-12 150 x 32 pixel format, LED Backlight available
28C010TRT1DE-15 1 Megabit (128K x 8-Bit) EEPROM
28C010TRT1DE-20 1 Megabit (128K x 8-Bit) EEPROM
28C010TRT1FB-15 1 Megabit (128K x 8-Bit) EEPROM
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