參數(shù)資料
型號： 28222-14
廠商： Conexant Systems, Inc.
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： 自動柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口
文件頁數(shù)： 71/161頁
文件大?。?/td> 1832K
代理商： 28222-14
FCTRL_IN[0]
CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.7 FIFO Port/UTOPIA Interface
100046C
Conexant
2-37
2.7 FIFO Port/UTOPIA Interface
The CN8223 has four bidirectional FIFO ports used to interface to the ATM layer
outside the chip. These four ports share FDAT_IN and FDAT_OUT 8-bit ports.
Each port has its own set of six control signals used for flow control and timing.
(Refer to
Figure 1-4
, for a diagram of the FIFO port/UTOPIA interface.)
Port 0 can be configured as a level 1 compliant UTOPIA port for connection
to other UTOPIA components. When UTOPIA mode is enabled, Ports 1, 2, and 3
are unused. The UTOPIA interface is detailed in
Section 2.7.5
.
2.7.1 FIFO Interface Inputs and Outputs
The four-port FIFO interface allows the connection of the CN8223 directly to
dual-port RAMs, FIFO RAMs, and other similar circuits. The FIFO interface pins
and their functions used for connection are listed in
Table 2-23
. Transmit FIFO
port timing for the 53-octet mode is shown in
Figure 2-16
. Detailed descriptions
of the transmit FIFO pin functions are given in
Table 2-24
. Receive FIFO port
timing for the 53-octet mode is shown in
Figure 2-17
. Detailed descriptions of the
receive FIFO pin functions are given in
Table 2-25
.
Table 2-23. FIFO Interface Pin Connections (1 of 2)
CN8223
Function
FDAT_IN[8:0]
Transmit Data with Parity
Port 0 Transmit Data FIFO Empty
FCTRL_IN[1]
Port 1 Transmit Data FIFO Empty
FCTRL_IN[2]
Port 2 Transmit Data FIFO Empty
FCTRL_IN[3]
Port 3 Transmit Data FIFO Empty
FCTRL_IN[4]
Port 0 Receive Data FIFO Full
FCTRL_IN[5]
Port 1 Receive Data FIFO Full
FCTRL_IN[6]
Port 2 Receive Data FIFO Full
FCTRL_IN[7]
Port 3 Receive Data FIFO Full
FDAT_OUT[8:0]
Receive Data with Parity
FCTRL_OUT[0]
Port 0 Receive Data Write Strobe
FCTRL_OUT[1]
Port 1 Receive Data Write Strobe
FCTRL_OUT[2]
Port 2 Receive Data Write Strobe
FCTRL_OUT[3]
Port 3 Receive Data Write Strobe
FCTRL_OUT[4]
Port 0 Receive Cell Invalid Indication
FCTRL_OUT[5]
Port 1 Receive Cell Invalid Indication
FCTRL_OUT[6]
Port 2 Receive Cell Invalid Indication
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