參數(shù)資料
型號： 28222-14
廠商： Conexant Systems, Inc.
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： 自動柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口
文件頁數(shù)： 145/161頁
文件大?。?/td> 1832K
代理商： 28222-14
Read Strobe Recovery Time
CN8223
4.0 Electrical and Mechanical Specifications
ATM Transmitter/Receiver with UTOPIA Interface
4.3 Timing
100046C
Conexant
4-11
4.3.3 FIFO Interface Timing
Table 4-7
and
Figure 4-6
display the timing requirements and characteristics of
the FIFO port interface. All times are in nanoseconds.
Table 4-7. FIFO Port Interface Timing
Name
Interval
Description
PHY Type 4-7
Min
PHY Type 0-3
Min
tptx,tprx
—
Transmit or Receive Clock Input Period
6.4
22.4
twdl
1
–
2
Write Strobe Low Pulse Width
4
×
tprx
2
×
tprx
twdr
2
–
4
Write Strobe Recovery Time
4
×
tprx
6
×
tprx
tfws
3
–
4
Full Input Setup to Write Strobe Falling Edge
4.0
4.0
tivws
5
–
7
Invalid Indication Stable before Write Strobe Rising Edge
3
×
tprx
2
×
tprx
tdows
6
–
7
Data Out Valid before Write Strobe Rising Edge
3
×
tprx
2
×
tprx
twsiv
12
–
13
Invalid Indication Stable after Write Strobe Rising Edge
3
×
tprx
4
×
tprx
twsdo
7
–
8
Data Out Valid after Write Strobe Rising Edge
3
×
tprx
4
×
tprx
tsyws
9
–
12
Receive Sync Valid before Write Strobe Rising Edge
3
×
tprx
2
×
tprx
twssy
12
–
14
Receive Sync Valid after Write Strobe Rising Edge
3
×
tprx
4
×
tprx
terr
10
–
11
Write Error Output Valid after Write Strobe Falling Edge
1.0
1.0
trdl
15
–
17
Read Strobe Low Pulse Width
4
×
tptx
2
×
tprx
trdr
17
–
20
4
×
tptx
6
×
tprx
tdirs
16
–
17
Data In Setup before Read Strobe Rising Edge
3.0
3.0
trsdi
17
–
18
Data In Hold after Read Strobe Rising Edge
2.0
2.0
tsyrs
19
–
21
Transmit Sync Valid before Read Strobe Rising Edge
3
×
tptx
2
×
tprx
trssy
21
–
22
Transmit Sync Valid after Read Strobe Rising Edge
4
×
tptx
4
×
tprx
tfsrs
23
–
26
Frame Sync Valid before Read Strobe Rising Edge
2
×
tptx
2
×
tprx
ters
24
–
26
Empty Input Setup to Read Strobe Rising Edge
4.0
4.0
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