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參數(shù)資料
| 型號(hào)： | 28222-14 |
| 廠商： | Conexant Systems, Inc. |
| 英文描述： | ATM Transmitter/Receiver with UTOPIA Interface |
| 中文描述： | 自動(dòng)柜員機(jī)發(fā)射機(jī)/接收機(jī)的UTOPIA接口 |
| 文件頁(yè)數(shù)： | 102/161頁(yè) |
| 文件大?。?/td> | 1832K |
| 代理商： | 28222-14 |
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3.0 Registers
CN8223
3.4 Transmit Control Registers
ATM Transmitter/Receiver with UTOPIA Interface
3-16
Conexant
100046C
FIFO input to pass.
0x04
–
0x07
—
CELL_GEN_x (Cell Generation Control Registers)
The CELL_GEN_x registers are located at addresses 0x04
–
0x07. Each of the four FIFO ports has its own ATM
Cell Generation Control Register, so x is 0, 1, 2 or 3. Cell generation is described in detail in
Section 2.6
. A
description of CELL_GEN_x Control Register addresses is provided in
Table 3-7
.
Table 3-7. CELL_GEN_x Control Register Addresses
Address
Register Name
Description
0x04
CELL_GEN_0
Cell Generation Control
—
Port 0 + UTOPIA
0x05
CELL_GEN_1
Cell Generation Control
—
Port 1
0x06
CELL_GEN_2
Cell Generation Control
—
Port 2
0x07
CELL_GEN_3
Cell Generation Control
—
Port 3
Bit
Field
Size
Name
Description
15, 14
2
Reserved
Set to 0.
13
1
Inhibit Single Cell
Generation
Inhibits cell transmission from the port for a single cell period and inserts an idle
cell in its place.
12
1
Error Payload CRC
Forces an error in the payload CRC-10 field. A single error is generated; then this
bit is cleared.
11
1
Error HEC
Forces an error in the ATM header HEC field. A single error is generated; then this
bit is cleared.
10
1
Disable Payload
CRC
Disables payload CRC-10 field generation and allows the existing field from the
9
1
Disable HEC
Disables the ATM header HEC field (octet 5) generation and allows the existing field
from the FIFO input to pass. The error mask in the TXFEAC_ERRPAT register
controls which bits are errored in the HEC field by XOR
’
ing this mask with the
calculated HEC, allowing the microprocessor to generate a specific number of
errors.
8
1
Insert CLP
Performs the same insertion function as Insert GFC (bit 4) for the CLP bit.
7
1
Insert PT
Performs the same insertion function as Insert GFC (bit 4) for the 3-bit payload
type field.
6
1
Insert VCI
Performs the same insertion function as Insert GFC (bit 4) for the 16-bit VCI field.
5
1
Insert VPI
Performs the same function as the Insert GFC (bit 4) for the 8-bit VPI field.
4
1
Insert GFC
Allows the 4-bit GFC field obtained from the FIFO interface to be overwritten with
the value programmed in the corresponding TX_HDR registers [0x0C
–
0x13]. This
bit is only valid in 52-, 53-, and 57-octet modes. In 48-octet mode, the GFC field is
always taken from the TX_HDR register.
3, 2
2
Port Priority
Allows the cell generator to assign four priority levels to the transmit source.
1, 0
2
Cell Generation
Mode
Selects the mode of operation for the generation circuit.
0 0 48 octet
0 1 52 octet
1 0 53 octet
1 1 57 octet
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