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| 型號(hào)： | 12CE673 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | HookUp/Lead Wire; Conductor Size AWG:18; No. Strands x Strand Size:65 x 36; Jacket Color:Black; Conductor Material:Copper; Jacket Material:Rubber; Leaded Process Compatible:Yes; Number of Conductors:1; Outer Diameter:0.144" RoHS Compliant: Yes |
| 中文描述： | 8引腳，8位CMOS微控制器與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 50/116頁(yè) |
| 文件大?。?/td> | 671K |
| 代理商： | 12CE673 |
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PIC12CE67X
DS40181B-page 50
Preliminary
1998 Microchip Technology Inc.
9.4
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
9.4.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
V
DD
has reached a high enough level for proper opera-
tion. To take advantage of the POR, just tie the MCLR
pin through a resistor to V
DD
. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for V
DD
is specified.
See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting"
9.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows V
DD
to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
The power-up time delay will vary from chip to chip due
to V
DD
, temperature, and process variation. See DC
parameters for details.
9.4.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 9-8,
Figure 9-9, and Figure 9-10 depict time-out sequences
on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-9). This is useful for testing purposes or to
synchronize more than one PIC12CE67X device oper-
ating in parallel.
Table 9-5 shows the reset conditions for all the regis-
ters.
9.4.5
POWER CONTROL (PCON)/STATUS
REGISTER
The power control/status register, PCON (address
8Eh) has one bit. See Figure 4-8 for register.
Bit1 is POR (Power-on Reset). It is cleared on a Power-
on Reset and is unaffected otherwise. The user set this
bit following a Power-on Reset. On subsequent resets
if POR is ‘0’, it will indicate that a Power-on Reset must
have occurred.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 9-4:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
Oscillator Configuration
Power-up
Wake-up from SLEEP
PWRTE = 0
72 ms + 1024T
OSC
72 ms
PWRTE = 1
1024T
OSC
—
XT, HS, LP
INTRC, EXTRC
1024T
OSC
—
POR
TO
PD
0
0
0
1
1
1
1
1
0
x
0
0
u
1
1
x
0
u
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
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