參數(shù)資料
型號: ZL50051
廠商: Zarlink Semiconductor Inc.
英文描述: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
中文描述: 8鉀通道數(shù)字開關(guān)高抖動容,單速率(8或16 Mbps)和64個輸入和輸出64
文件頁數(shù): 62/67頁
文件大?。?/td> 562K
代理商: ZL50051
ZL50051/3
Data Sheet
62
Zarlink Semiconductor Inc.
Note 1:
High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge
C
L
.
Note 2:
There must be a minimum of 30 ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a
minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next
access).
Non-Multiplexed Microprocessor Port Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
CS setup from DS falling
t
CSS
t
RWS
t
ADS
t
CSH
t
RWH
t
ADH
t
RDS
0
ns
2
R/W setup from DS falling
9
ns
3
Address setup from DS falling
9
ns
4
CS hold after DS rising
0
ns
5
R/W hold after DS rising
9
ns
6
Address hold after DS rising
9
ns
7
Data setup from DTA Low on Read
5
12
ns
ns
Memory Read
Register Read
C
L
= 60 pF
C
L
= 60 pF,
R
L
= 1 k
Note 1
8
Data hold on read
t
RDH
4.5
ns
9
Data setup on write
t
WDS
t
WDH
t
AKD
9
ns
10
Data hold on write
9
ns
11
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
88
80
ns
ns
C
L
= 60 pF
C
L
= 60 pF
12
Acknowledgment Hold Time
t
AKH
11
ns
C
L
= 60 pF,
R
L
= 1 k,
Note 1
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