參數(shù)資料
型號(hào): ZL50051
廠商: Zarlink Semiconductor Inc.
英文描述: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
中文描述: 8鉀通道數(shù)字開關(guān)高抖動(dòng)容,單速率(8或16 Mbps)和64個(gè)輸入和輸出64
文件頁數(shù): 46/67頁
文件大?。?/td> 562K
代理商: ZL50051
ZL50051/3
Data Sheet
46
Zarlink Semiconductor Inc.
13.6 Backplane Output Advancement Registers (BOAR0 - BOAR31)
Addresses 00A3
H
to 00C2
H
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR31) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. The possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
The
BOAR0
to
BOAR31
registers are configured as follows:
Table 21 - Backplane Output Advancement Register (BOAR) Bits
13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
BOARn Bit
(where n = 0 to 31)
Name
Reset
Value
Description
15:2
Reserved
0
Reserved
Must be set to 0 for normal operation
1:0
BOA[1:0]
0
Backplane Output Advancement Value
Backplane Output Advancement
Corresponding
Advancement Bits
Clock Rate 131.072 MHz
BOA1
BOA0
0 (Default)
0
0
-2 cycles (~15 ns)
0
1
-4 cycles (~31 ns)
1
0
-6 cycles (~46 ns)
1
1
Table 22 - Backplane Output Advancement (BOAR) Programming Table
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