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參數(shù)資料
| 型號： | ZL50051 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| 中文描述： | 8鉀通道數(shù)字開關(guān)高抖動容，單速率（8或16 Mbps）和64個輸入和輸出64 |
| 文件頁數(shù)： | 30/67頁 |
| 文件大小： | 562K |
| 代理商： | ZL50051 |
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ZL50051/3
Data Sheet
30
Zarlink Semiconductor Inc.
8.3 Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after
power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 13 and Table 14 for details of the Control
Register and Block Programming Register values, respectively.
8.3.1 Memory Block Programming Procedure:
Set the
MBP
bit in the Control Register from LOW to HIGH.
Set the
BPE
bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD[2:0]
, of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection
Memory. The remaining bit positions are loaded with zeros as shown in Table 5.
Table 5 - Local Connection Memory in Block Programming Mode
The Backplane Block Programming data bits,
BBPD[2:0]
, of the Block Programming Register, will be loaded into
bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as
shown in Table 6.
Table 6 - Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit,
BPE
will be automatically reset LOW within 125
μ
s, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by clearing the
BPE
bit of the
Block Programming Register or the
MBP
bit of the Control Register.
Note that the default values (LOW) of
LBPD[2:0]
and
BBPD[2:0]
of the Block Programming Register, following a
device reset, can be used.
During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS
pins, irrespective of the values in bits[14:13] of the connection memory.
Source Stream Bit Rate
Source Stream No.
Source Channel No.
8 Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:127
16 Mbps
Bits[12:8]
legal values 0:15
Bits[7:0]
legal values 0:255
Table 4 - Local and Backplane Connection Memory Configuration
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBPD2
LBPD1
LBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BBPD2
BBPD1
BBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
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| ZL50053QCC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 512MBPS 1.8V 256LQFP - Trays |
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