參數(shù)資料
型號: ZL50051
廠商: Zarlink Semiconductor Inc.
英文描述: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
中文描述: 8鉀通道數(shù)字開關(guān)高抖動容,單速率(8或16 Mbps)和64個(gè)輸入和輸出64
文件頁數(shù): 45/67頁
文件大?。?/td> 562K
代理商: ZL50051
ZL50051/3
Data Sheet
45
Zarlink Semiconductor Inc.
13.5 Local Output Advancement Registers (LOAR0 to LOAR31)
Addresses 0083
H
to 00A2
H
.
Thirty-two Local Output Advancement Registers (LOAR0 to LOAR31) allow users to program the output
advancement for output data streams LSTo0 to LSTo31. The possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
The
LOAR0
to
LOAR31
registers are configured as follows:
Table 19 - Local Output Advancement Register (LOAR) Bits
13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
LOARn Bit
(where n = 0 to 31)
Name
Reset
Value
Description
15:2
Reserved
0
Reserved
Must be set to 0 for normal operation
1:0
LOA[1:0]
0
Local Output Advancement Value
Local Output Advancement
Corresponding
Advancement Bits
Clock Rate 131.072 MHz
LOA1
LOA0
0 (Default)
0
0
-2 cycles (~15 ns)
0
1
-4 cycles (~31 ns)
1
0
-6 cycles (~46 ns)
1
1
Table 20 - Local Output Advancement (LOAR) Programming Table
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