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參數(shù)資料
| 型號： | ZL50051 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| 中文描述： | 8鉀通道數(shù)字開關高抖動容，單速率（8或16 Mbps）和64個輸入和輸出64 |
| 文件頁數(shù)： | 40/67頁 |
| 文件大?。?/td> | 562K |
| 代理商： | ZL50051 |
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ZL50051/3
Data Sheet
40
Zarlink Semiconductor Inc.
13.2 Block Programming Register (BPR)
Address 0001
H
.
The Block Programming Register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the BPR register must
be defined in the same write operation.
The BPE bit is set HIGH to commence the block programming operation. Programming is completed in one frame
period and may be initiated at any time within a frame. The BPE bit returns to LOW to indicate that the block
programming function has completed.
When BPE is HIGH, no other bits of the BPR register may be changed for at least a single frame period, except to
abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the
Control Register bit, MBP, to LOW.
The
BPR
register is configured as follows:
Table 14 - Block Programming Register Bits
Bit
Name
Reset
Value
Description
15:7
Reserved
0
Reserved
Must be set to 0 for normal operation
6:4
BBPD[2:0]
0
Backplane Block Programming Data
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated.
When the MBP bit in the Control Register (CR) is set HIGH and BPE (in this
register) is set HIGH, the contents of bits BBPD[2:0] are loaded into bits 15-13,
respectively, of the BCM. Bits 12-0 of the BCM are set LOW.
3:1
LBPD[2:0]
0
Local Block Programming Data
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated.
When the MBP bit in the Control Register is set HIGH and BPE (in this register)
is set HIGH, the contents of bits LBPD[2:0] are loaded into bits 15-13,
respectively, of the LCM. Bits 12-0 of the LCM are set LOW.
0
BPE
0
Block Programming Enable
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125
μ
s, upon completion of programming.
Set LOW to abort the programming operation.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50051GAC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 512MBPS 1.8V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA 制造商:Microsemi Corporation 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA |
| ZL50051GAG2 | 制造商:Microsemi Corporation 功能描述:PB FREE8KDXHIJIT TOLSNGLERATE 8/16MBPS17 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA 制造商:Microsemi Corporation 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA |
| ZL50052 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs |
| ZL50052GAC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 524.288MBPS 1.8V 196BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA 制造商:Microsemi Corporation 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA |
| ZL50053QCC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 512MBPS 1.8V 256LQFP - Trays |
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