參數(shù)資料
型號(hào)： ZL50051
廠商： Zarlink Semiconductor Inc.
英文描述： 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
中文描述： 8鉀通道數(shù)字開關(guān)高抖動(dòng)容，單速率（8或16 Mbps）和64個(gè)輸入和輸出64
文件頁(yè)數(shù)： 22/67頁(yè)
文件大?。?/td> 562K
代理商： ZL50051
ZL50051/3
Data Sheet
22
Zarlink Semiconductor Inc.
Figure 8 illustrates the input and output frame pulse alignment. The t
FBOS
is the offset between the input frame
pulse, FP8i, and the generated output frame pulse, FP8o. Refer to the “AC Electrical Characteristics”, on page 52.
Note that although this figure shows the traditional setups of the frame pulses and clocks for both ST-BUS and
GCI-Bus configurations, the devices can be configured to accept/generate double-width frame pulses (if the FPW
bit in the Control Register is set) as well as to use the opposite clock edge for frame-boundary determination (using
the C8IPOL and COPOL bits in the Control Register). See the timing diagrams in “AC Electrical Characteristics”, on
page 52 for all of the available configurations.
2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
To improve the jitter tolerance of the ZL50051/3, a Frame Boundary Discriminator (FBD) circuit was added to the
device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled.
The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits
FBD_MODE[2:0] are set to 000
B
, the FBD is set to handle lower frequency jitter only (<8 kHz). When bits
FBD_MODE[2:0] are set to 111
B
, the FBD can handle both low frequency and high frequency jitter. All other values
are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set
HIGH, bits FBD_MODE[2:0] should be set to 111
B
to improve the high frequency jitter handling capability.
To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be
optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by
programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused
by jitter. There are, however, some cases where data experiences more delay than the timing signals. A common
example occurs when multiple data lines are tied together to form bi-directional buses. The large bus loading may
cause data to be delayed. If this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. The
optimum sampling point is dependent on the application. The user should optimize the sampling point to achieve
the best jitter tolerance performance.
2.5 Input Clock Jitter Tolerance
Input clock jitter tolerance depends on the data rate. In general, the higher the data rate, the smaller the jitter
tolerance is, because the period of a bit cell is shorter, and the sampling point variation allowance is smaller.
Jitter tolerance can not be accurately represented by just one number. Jitter of the same amplitude but different
frequency spectrum can have different effect on the operation of a device. For example, a device that can tolerate
20 ns of jitter of 10 kHz frequency may only be able to tolerate 10 ns of jitter of 1 MHz frequency. Therefore, jitter
tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the
carrier frequency. In the case of the ZL50051/3, the input clock is 8.192 MHz, and the jitter associated with this
clock can have the highest frequency component at 4.096 MHz.
For the above reasons, jitter tolerance of the ZL50051/3 has been characterized at 16.384 Mbps. The lower data
rate (8.192 Mbps) will have the same or better tolerance than that of the 16.384 Mbps operation. Tolerance of jitter
of different frequencies are shown in the “AC Electrical Characteristics” section, table “Input Clock Jitter Tolerance”
on page 61. The Jitter Tolerance Improvement Circuit was enabled (Control Register, bit FBDEN set HIGH, and bits
FBD_MODE[2:0] set to 111
B
), and the sampling point was optimized.
3.0 Input and Output Offset Programming
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
3.1 Input Offsets
Control of the Input Bit Delay allows each input stream to have a different frame boundary with respect to the
master frame pulse, FP8i. Each input stream can be individually delayed by up to 7 3/4 bits with a resolution of 1/4
bit of the bit period.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50051GAC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 512MBPS 1.8V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA 制造商:Microsemi Corporation 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA
ZL50051GAG2 制造商:Microsemi Corporation 功能描述:PB FREE8KDXHIJIT TOLSNGLERATE 8/16MBPS17 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA 制造商:Microsemi Corporation 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA
ZL50052 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
ZL50052GAC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 524.288MBPS 1.8V 196BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA 制造商:Microsemi Corporation 功能描述:IC DIGITAL SWITCH 8K CH 196PBGA
ZL50053QCC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 512MBPS 1.8V 256LQFP - Trays
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