參數(shù)資料
型號： ZL50015
廠商： Zarlink Semiconductor Inc.
英文描述： Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述： 增強1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán)
文件頁數(shù)： 88/122頁
文件大?。?/td> 926K
代理商： ZL50015
ZL50015
Data Sheet
88
Zarlink Semiconductor Inc.
When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits
PCC0 and PCC1 from connection memory are used to select the per-channel tristate, message or BER test mode
as shown in Table 52 on page 88.
24.3 Connection Memory High (CM_H) Bit Assignment
Connection memory high provides the detailed information required for
μ
-law and A-law conversion. ICL and OCL
bits describe the Input Coding Law and the Output Coding Law, respectively. They are used to select the expected
PCM coding laws for the connection, on the TDM inputs, and on the TDM outputs. The V/D bit is used to select the
class of coding law. If the V/D bit is cleared (to select a voice connection), the ICL and OCL bits select between
A-law and
μ
-law specifications related to G.711 voice coding. If the V/D bit is set (to select a data connection), the
ICL and OCL bits select between various bit inverting protocols. These coding laws are illustrated in the following
table. If the ICL is different than the OCL, all data bytes passing through the switch on that particular connection are
translated between the indicated laws. If the ICL and the OCL are the same, no coding law translation is performed.
Bit
Name
Description
15
UAEN
Conversion between
μ
-law and A-law Enable (Message mode only)
When this bit is low, message mode has no
μ
-law/A-law conversion. Connec-
tion memory high will be ignored.
When this bit is high, message mode has
μ
-law/A-law conversion, and con-
nection memory high controls the conversion method.
14 - 11
Unused
Reserved
In normal functional mode, these bits
MUST
be set to zero.
10 - 3
MSG7 - 0
Message Data Bits
8-bit data for the message mode. Not used in the per-channel tristate and
BER test modes.
2 - 1
PCC1 - 0
Per-Channel Control Bits
These two bits control the corresponding entry’s value on the STio stream
.
0
CMM = 1
Connection Memory Mode = 1
If this is high, the connection memory is in the per-channel control mode
which is per-channel tristate, per-channel message mode or per-channel BER
mode.
Note: For proper
μ
-
law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 52 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UA
EN
0
0
0
0
MSG
7
MSG
6
MSG
5
MSG
4
MSG
3
MSG
2
MSG
1
MSG
0
PCC
1
PCC
0
CMM
=1
PC
C1
PC
C0
Channel Output Mode
0
0
Per Channel Tristate
0
1
Message Mode
1
0
BER Test Mode
1
1
Reserved
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相關代理商/技術參數(shù)
參數(shù)描述
ZL50015_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
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ZL50015QCC1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
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