參數(shù)資料
型號: ZL50015QCC1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BJC, LQFP-256
文件頁數(shù): 1/122頁
文件大小: 926K
代理商: ZL50015QCC1
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
1024 channel x 1024 channel non-blocking digital
Time Division Multiplex (TDM) switch at 4.096,
8.192 and 16.384 Mbps or using a combination of
ports running at 2.048, 4.096, 8.192 and
16.384 Mbps
16 serial TDM input, 16 serial TDM output
streams
Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 4E
specifications
Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
Output streams can be configured as bi-
directional for connection to backplanes
Per-stream input and output data rate conversion
selection at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps
or 16.384 Mbps. Input and output data rates can
differ
Per-stream high impedance control outputs
(STOHZ) for 8 output streams
Per-stream input bit delay with flexible sampling
point selection
July 2005
Ordering Information
256 Ball PBGA
256 Lead LQFP
256 Lead LQFP*
*Pb Free Matte Tin
-40
°
C to +85
°
C
ZL50015GAC
ZL50015QCC
ZL50015QCC1
Trays
Trays
Trays
ZL50015
Enhanced 1 K Digital Switch with
Stratum 4E DPLL
Data Sheet
Figure 1 - ZL50015 Functional Block Diagram
Data Memory
Internal Registers &
Microprocessor Interface
Input Timing
Output HiZ
Control
Test Port
OSC
DPLL
S/P Converter
STOHZ[7:0]
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
STio[15:0]
ODE
RESET
V
SS
V
DD_IO
V
DD_CORE
FPi
CKi
REF0
REF1
REF2
REF3
O
O
Connection Memory
M
D
C
D
A
T
T
T
T
T
Output Timing
STi[15:0]
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
I
P/S Converter
D
R
OSC_EN
MODE_4M0
MODE_4M1
V
DD_IOA
V
DD_COREA
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
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