參數(shù)資料
型號： ZL50015
廠商： Zarlink Semiconductor Inc.
英文描述： Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述： 增強1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán)
文件頁數(shù)： 111/122頁
文件大?。?/td> 926K
代理商： ZL50015
ZL50015
Data Sheet
111
Zarlink Semiconductor Inc.
Figure 45 - FPo3 and CKo3 (32.768 MHz) Timing Diagram
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
-
FPo3 and CKo3 (32.768 MHz) Timing (Master Mode, Divided Slave Mode, or Multiplied Slave
Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
FPo3 Output Pulse Width
FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
CKo3 Output Clock Period
CKo3 Output High Time
CKo3 Output Low Time
CKo3 Output Rise/Fall Time
t
FPW3
t
FODF3
27
10
30.5
34
18
ns
ns
C
L
= 30 pF
3
t
FODR3
12
21
ns
4
5
6
7
t
CKP3
t
CKH3
t
CKL3
t
rCK3
, t
fCK3
27
12
12
30.5
34
19
19
5
ns
ns
ns
ns
C
L
= 30 pF
AC Electrical Characteristics
- FPo3 and CKo3 (32.768 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
FPo3 Output Pulse Width
FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
CKo3 Output Clock Period
CKo3 Output High Time
CKo3 Output Low Time
CKo3 Output Rise/Fall Time
t
FPW3
t
FODF3
27
12
30.5
34
19
ns
ns
C
L
= 30 pF
3
t
FODR3
12
19
ns
4
5
6
7
t
CKP3
t
CKH3
t
CKL3
t
rCK3
, t
fCK3
17
5
12
30.5
44
29
18
5
ns
ns
ns
ns
C
L
= 30 pF
t
FPW3
t
FODR3
t
FODF3
FPo3
CKo3
t
CKL3
t
CKH3
t
CKP3
t
rCK3
t
fCK3
Output Frame Boundary
V
CT
V
CT
相關PDF資料
PDF描述
ZL50015GAC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCC1 Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL
ZL50018GAC 2 K Digital Switch with Enhanced Stratum 3 DPLL
相關代理商/技術參數(shù)
參數(shù)描述
ZL50015_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015GAC 制造商:Microsemi Corporation 功能描述:Switch Fabric 1K x 1K 1.8V/3.3V 256-Pin BGA Tray 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays
ZL50015GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays
ZL50015QCC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256LQFP - Trays
ZL50015QCC1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
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