參數(shù)資料
型號： ZL50015
廠商： Zarlink Semiconductor Inc.
英文描述： Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述： 增強1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán)
文件頁數(shù)： 66/122頁
文件大小： 926K
代理商： ZL50015
ZL50015
Data Sheet
66
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 0
CFN15 - 0
Center Frequency Number (CFN) Lower 16 Bits:
The total binary value of these bits
and the CFRU register bits defines the output center frequency number according to the
following formula:
where, f
OUT
is desired output center frequency, while f
MCLK
is frequency of DPLL master
clock. For given master clock frequency of 100 MHz, and desired output center fre-
quency of 65.536 MHz, the CFN has the value of:
The register contents should be changed only if compensation for input oscillator (or
crystal) frequency offset is required.
e.g., if master clock frequency is off by +20 ppm (100.002 MHz -> 5 times multiplied c20i
of 20.0004 MHz), the CFN should be programmed to be:
The default value of this register
SHOULD NOT
be changed in any other circumstances.
Table 28 - Centre Frequency Register - Lower 16 Bits (CFRL)
Bit
Name
Description
15 - 10
Unused
Reserved.
In normal functional mode, these bits
MUST
be set to zero.
9 - 0
CFN25 - 16
Center Frequency Number (CFN) Upper 10 Bits:
The total binary value of these bits
and the CFRL register bits represents the center frequency number (CFN) explained
under CFRL register bits explanation.
The default value of this register should be changed only if compensation for input oscil-
lator (or crystal) frequency offset is required, and
SHOULD NOT
be changed in any other
circumstances.
Table 29 - Centre Frequency Register - Upper 10 Bits (CFRU)
External Read/Write Address: 0042
H
Reset Value: 16B1
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFN
15
CFN
14
CFN
13
CFN
12
CFN
11
CFN
10
CFN
9
CFN
8
CFN
7
CFN
6
CFN
5
CFN
4
CFN
3
CFN
2
CFN
1
CFN
0
f
OUT
2
CFN
f
MCLK
×
=
CFN
2
26
100MHz
65.536MHz
×
2
26
0.65536
×
43980465
29F16B1
H
=
=
=
=
CFN
2
26
100.002MHz
-65.536MHz
×
2
26
0.65534689
×
43979585
29F1341
H
=
=
=
=
External Read/Write Address: 0043
H
Reset Value: 029F
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
CFN
25
CFN
24
CFN
23
CFN
22
CFN
21
CFN
20
CFN
19
CFN
18
CFN
17
CFN
16
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ZL50015GAC Enhanced 1 K Digital Switch with Stratum 4E DPLL
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相關代理商/技術參數(shù)
參數(shù)描述
ZL50015_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015GAC 制造商:Microsemi Corporation 功能描述:Switch Fabric 1K x 1K 1.8V/3.3V 256-Pin BGA Tray 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays
ZL50015GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays
ZL50015QCC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256LQFP - Trays
ZL50015QCC1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
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