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參數(shù)資料
| 型號(hào)： | ZL50015 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| 中文描述： | 增強(qiáng)1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán) |
| 文件頁(yè)數(shù)： | 68/122頁(yè) |
| 文件大?。?/td> | 926K |
| 代理商： | ZL50015 |
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ZL50015
Data Sheet
68
Zarlink Semiconductor Inc.
Table 32 - Lock Detector Interval Register (LDIR) Bits
Bit
Name
Description
15 - 0
LDT15 - 0
Lock Detect Threshold Bits
The binary value of these bits defines the upper limit of the absolute phase from the
phase detector output for lock detection.
When the value of the absolute phase is less than or equal to LDT for duration of time
defined by the LDIR register, the DPLL locks.
When the value of the absolute phase is greater than LDT for duration of time defined by
the LDIR register divided by 256, the DPLL does not lock.
Note: LDT should be calculated as per the maximum expected amplitude of jitter on the active input reference
using the following formula:
LDT = MAX_EXP_JITTER (ns) x 2
15.2 (ns)
Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e., 10 x 488.2 ns = 4882 ns)
(assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15.2)
x 2 = 642 = 0282
H
Table 31 - Lock Detector Threshold Register (LDTR) Bits
Bit
Name
Description
15 - 0
LDI15 - 0
Lock Detector Interval Bits
The binary value of these bits defines the time interval that the output phase detector
must be below the lock detect threshold to declare lock. Unsigned representation of the
LDI bits is defined in 4 ms intervals.
External Read/Write Address: 0047
H
Reset Value: 000F
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDT
15
LDT
14
LDT
13
LDT
12
LDT
11
LDT
10
LDT
9
LDT
8
LDT
7
LDT
6
LDT
5
LDT
4
LDT
3
LDT
2
LDT
1
LDT
0
External Read/Write Address: 0048
H
Reset Value: 2C00
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDI
15
LDI
14
LDI
13
LDI
12
LDI
11
LDI
10
LDI
9
LDI
8
LDI
7
LDI
6
LDI
5
LDI
4
LDI
3
LDI
2
LDI
1
LDI
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50015GAC | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015QCC | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015QCC1 | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50018 | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50018GAC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50015_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015GAC | 制造商:Microsemi Corporation 功能描述:Switch Fabric 1K x 1K 1.8V/3.3V 256-Pin BGA Tray 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays |
| ZL50015GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays |
| ZL50015QCC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256LQFP - Trays |
| ZL50015QCC1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL |
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