參數(shù)資料
型號: ZL50015
廠商: Zarlink Semiconductor Inc.
英文描述: Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述: 增強1K的數(shù)字交換與地層4E條數(shù)字鎖相環(huán)
文件頁數(shù): 109/122頁
文件大?。?/td> 926K
代理商: ZL50015
ZL50015
Data Sheet
109
Zarlink Semiconductor Inc.
Figure 43 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
-
FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
FPo1 Output Pulse Width
FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
CKo1 Output Clock Period
CKo1 Output High Time
CKo1 Output Low Time
CKo1 Output Rise/Fall Time
t
FPW1
t
FODF1
117
56
122
127
66
ns
ns
C
L
= 30 pF
3
t
FODR1
56
66
ns
4
5
6
7
t
CKP1
t
CKH1
t
CKL1
t
rCK1
, t
fCK1
117
56
56
122
127
66
66
5
ns
ns
ns
ns
C
L
= 30 pF
AC Electrical Characteristics
-
FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
FPo1 Output Pulse Width
FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
CKo1 Output Clock Period
CKo1 Output High Time
CKo1 Output Low Time
CKo1 Output Rise/Fall Time
t
FPW1
t
FODF1
106
56
122
127
66
ns
ns
C
L
= 30 pF
3
t
FODR1
46
66
ns
4
5
6
7
t
CKP1
t
CKH1
t
CKL1
t
rCK1
, t
fCK1
106
46
46
122
148
87
66
5
ns
ns
ns
ns
C
L
= 30 pF
t
FPW1
t
FODR1
t
FODF1
FPo1/FPo3
CKo1/CKo3
t
CKL1
t
CKH1
t
CKP1
t
rCK1
t
fCK1
Output Frame Boundary
V
CT
V
CT
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