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參數資料
| 型號： | ZL30102QDG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64 |
| 文件頁數： | 37/50頁 |
| 文件大?。?/td> | 481K |
| 代理商： | ZL30102QDG |
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ZL30102
Data Sheet
37
Zarlink Semiconductor Inc.
6.5 Clock Redundancy System Architecture
Carrier-Class Telecommunications Equipment deployed in today’s networks guarantee better than 99.999%
operational availability (equivalent to less than 7 minutes of downtime per year). This high level of uninterrupted
service is achieved by fully redundant architectures with hot swappable cards like an ECTF H.110 compliant
system. Timing for these types of systems can be generated by the ZL30102 which supports primary/secondary
master timing protection switching.
The architecture shown in Figure 23 is based on the ZL30102 being deployed on two separate timing cards; the
primary master timing card and the secondary master timing card. In normal operation the primary master timing
card receives synchronization from the network and provides timing for the whole system. The redundant
secondary master timing card is phase locked to the backplane clock and frame pulse through its REF2 and
REF2_SYNC inputs. These two designated inputs allow the secondary master timing card to track the primary
master timing card clocks with minimal phase skew. When the primary master timing card fails unexpectedly (this
failure is not related to reference failure) then all switch cards or line cards will detect this failure and they will switch
to the timing supplied by the secondary master timing card. The secondary master timing card will be promoted to
primary master and switch from using the REF2 and REF2_SYNC inputs to one of the REF0 or REF1 inputs.
Figure 23 - Typical Clocking Architecture of an ECTF H.110 System
ZL30102
REF0
REF1
REF2
Primary Master Timing Card
Backplane
REF2_SYNC
C8o
F8o
CT_C8_A
CT_FRAME_A
CT_C8_B
CT_FRAME_B
CT_NETREF_1
CT_NETREF_2
SEC_MSTR
Master/Slave
Control
0
ZL30102
REF0
REF1
REF2
Secondary Master Timing Card
REF2_SYNC
C8o
F8o
SEC_MSTR
Master/Slave
Control
1
Switch Card or Line Card
Switch Card or Line Card
相關PDF資料 |
PDF描述 |
|---|---|
| ZL30105QDG1 | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105 | Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA |
| ZL30105QDG | Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA |
| ZL30106QDG1 | SONET/SDH/PDH Network Interface DPLL |
| ZL30106 | SONET/SDH/PDH Network Interface DPLL |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ZL30102QDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays |
| ZL30105 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 |
| ZL30105_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105QDG | 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk |
| ZL30105QDG1 | 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer |
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