參數(shù)資料
型號(hào)： ZL30102QDG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64
文件頁數(shù)： 10/50頁
文件大?。?/td> 481K
代理商： ZL30102QDG
ZL30102
Data Sheet
10
Zarlink Semiconductor Inc.
19
RST
Reset (Input).
A logic low at this input resets the device. On power up, the RST pin
must be held low for a minimum of 300 ns after the power supply pins have reached
the minimum supply voltage. When the RST pin goes high, the device will transition
into a Reset state for 3 ms. In the Reset state all outputs will be forced into high
impedance.
20
OSCo
Oscillator Master Clock (Output).
For crystal operation, a 20 MHz crystal is connected
from this pin to OSCi. This output is not suitable for driving other devices. For clock
oscillator operation, this pin must be left unconnected.
21
OSCi
Oscillator Master Clock (Input).
For crystal operation, a 20 MHz crystal is connected
from this pin to OSCo. For clock oscillator operation, this pin must be connected to a
clock source.
22
IC
Internal Connection.
Leave unconnected.
23
GND
Ground.
0 V
24
NC
No internal bonding Connection.
Leave unconnected.
25
V
DD
Positive Supply Voltage.
+3.3 V
DC
nominal
Output Selection (Input).
This input selects the signals on the combined output clock
and frame pulse pins, see Table 3 on page 21.
26
OUT_SEL
27
IC
Internal Connection.
Connect this pin to ground.
28
IC
Internal Connection.
Connect this pin to ground.
29
AV
DD
C6o
Positive Analog Supply Voltage.
+3.3 V
DC
nominal
Clock 6.312 MHz (Output).
This output is used in DS2 applications.
30
31
C3o
Clock 3.088 MHz (Output).
This output is used in DS1 applications.
32
C1.5o
Clock 1.544 MHz (Output).
This output is used in DS1 applications.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
33
AGND
Analog Ground.
0 V
34
AGND
Analog Ground.
0 V
35
AV
CORE
AV
DD
AV
DD
NC
Positive Analog Supply Voltage.
+1.8 V
DC
nominal
Positive Analog Supply Voltage.
+3.3 V
DC
nominal
Positive Analog Supply Voltage.
+3.3 V
DC
nominal
No internal bonding Connection.
Leave unconnected.
36
37
38
39
NC
No internal bonding Connection.
Leave unconnected.
40
AGND
Analog Ground.
0 V
41
AGND
Analog Ground.
0 V
42
C4/C65o
Clock 4.096 MHz or 65.536 MHz (Output).
This output is used for ST-BUS operation at
2.048 Mbit/s, 4.096 Mbit/s or 65.536 MHz (ST-BUS 65.536 Mbit/s). The output frequency
is selected via the OUT_SEL pin, see Table 3 on page 21.
Pin #
Name
Description
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ZL30102QDG1 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays
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ZL30105_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
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