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參數(shù)資料
| 型號： | ZL30102QDG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 32/50頁 |
| 文件大小： | 481K |
| 代理商： | ZL30102QDG |
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ZL30102
Data Sheet
32
Zarlink Semiconductor Inc.
5.0 Measures of Performance
The following are some PLL performance indicators and their corresponding definitions.
5.1 Jitter
Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander
is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low
frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or
20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter
numbers, not cycle-to-cycle jitter.
5.2 Jitter Generation (Intrinsic Jitter)
Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter generation
may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by
measuring the output jitter of the device. Jitter is usually measured with various bandlimiting filters depending on
the applicable standards.
5.3 Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied
jitter magnitude and jitter frequency depends on the applicable standards.
5.4 Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
For the Zarlink digital PLLs two internal elements determine the jitter attenuation; the internal low pass loop filter
and the phase slope limiter. The phase slope limiter limits the output phase slope to, for example, 61
μ
s/s.
Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the
maximum output phase slope will be limited (i.e., attenuated).
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for
large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (for example 75% of the specified maximum tolerable input jitter).
5.5 Frequency Accuracy
The Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode.
5.6 Holdover Accuracy
Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external
reference signal, but is operating using storage techniques. For the ZL30102, the storage value is determined while
the device is in Normal Mode and locked to an external reference signal.
相關(guān)PDF資料 |
PDF描述 |
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| ZL30105QDG1 | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105 | Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA |
| ZL30105QDG | Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30102QDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays |
| ZL30105 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 |
| ZL30105_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105QDG | 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk |
| ZL30105QDG1 | 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer |
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