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參數(shù)資料
| 型號： | ZL30105QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 1/52頁 |
| 文件大?。?/td> | 1097K |
| 代理商： | ZL30105QDG1 |
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1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between the master-clock
and the redundant slave-clock
Supports ITU-T G.813 option 1, G.823 for
2048 kbit/s and G.824 for 1544 kbit/s interfaces
Supports Telcordia GR-1244-CORE Stratum
3/4/4E
Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
Provides a range of clock outputs: 1.544 MHz
(DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz,
and 19.44 MHz (SDH), and either 4.096 MHz and
8.192 MHz or 32.768 MHz and 65.536 MHz, and a
choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
Holdover frequency accuracy of 1x10
-8
Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz
Less than 24 ps
rms
intrinsic jitter on the 19.44 MHz
output clock, compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications
Less than 0.6 ns
pp
intrinsic jitter on all output
clocks and frame pulses
Manual or Automatic hitless reference switching
between any combination of valid input reference
frequencies
Provides Lock, Holdover and selectable Out of
Range indication
Simple hardware control interface
Selectable external master clock source: Clock
Oscillator or Crystal
Applications
Synchronization and timing control for multi-trunk
SDH and T1/E1 systems such as DSLAMs,
Gateways and PBXs
Clock and frame pulse source for
AdvancedTCA- and other time division
multiplex (TDM) buses
November 2005
Ordering Information
ZL30105QDG
ZL30105QDG1
64 pin TQFP
64 pin TQFP* Trays Bake & Drypack
* Pb Free Matte Tin
Trays
-40
°
C to +85
°
C
ZL30105
T1/E1/SDH Stratum 3 Redundant System Clock
Synchronizer for AdvancedTCA and H.110
Data Sheet
Figure 1 - Functional Block Diagram
Reference
Monitor
Mode
Control
Virtual
Reference
IEEE
1149.1a
TIE
Corrector
Enable
State Machine
Frequency
Select
MUX
TIE
Corrector
Circuit
MODE_SEL1:0
TCK
REF1
REF2
RST
REF_SEL1:0
TIE_CLR
OSCo
OSCi
Master Clock
TDO
REF0
TDI TMS
TRST
HOLDOVER
HMS
LOCK
REF_FAIL0
REF_FAIL1
REF_FAIL2
DPLL
OUT_SEL2
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
E1
Synthesizer
DS1
Synthesizer
MUX
SDH
Synthesizer
Programmable
Synthesizer
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
FASTLOCK
REF2_SYNC
SEC_MSTR
APP_SEL1:0
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