參數(shù)資料
型號(hào): ZL30105QDG1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁(yè)數(shù): 44/52頁(yè)
文件大?。?/td> 1097K
代理商: ZL30105QDG1
ZL30105
Data Sheet
44
Zarlink Semiconductor Inc.
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Figure 29 - DS1 Output Timing Referenced to F8/F32o
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Figure 30 - SDH Output Timing Referenced to F8/F32o
AC Electrical Characteristics* - DS1 output timing (see Figure 29).
Characteristics
Sym.
Min.
Max.
Units
Notes
1
C1.5o delay
t
C1.5D
t
C1.5L
t
C3D
t
C3L
t
OR
t
OF
-0.6
0.6
ns
outputs loaded
with 30 pF
2
C1.5o pulse width low
323.1
324.0
ns
3
C3o delay
-0.7
0.5
ns
4
C3o pulse width low
161.1
162.0
ns
5
Output clock and frame pulse rise time
1.1
2.0
ns
6
Output clock and frame pulse fall time
1.2
2.3
ns
AC Electrical Characteristics* - SDH output timing (see Figure 30).
Characteristics
Sym.
Min.
Max.
Units
Notes
1
C19o delay
t
C19D
t
C19L
t
F2kD
t
F2kH
t
OR
t
OF
-1.0
0.5
ns
outputs loaded
with 30 pF
2
C19o pulse width low
25.0
25.8
ns
3
F2ko delay
25.0
26.6
ns
4
F2ko pulse width high
51.1
51.8
ns
5
Output clock and frame pulse rise time
1.1
2.0
ns
6
Output clock and frame pulse fall time
1.2
2.3
ns
F8_32o
t
C1.5D
t
C1.5L
C1.5o
t
C3D
t
C3L
C3o
F8_32o
t
C19D
t
F2D
C19o
F2ko
t
C19L
t
F2kH
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