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參數(shù)資料
| 型號： | ZL30105QDG1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 1097K |
| 代理商： | ZL30105QDG1 |
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ZL30105
Data Sheet
32
Zarlink Semiconductor Inc.
5.7
Pull-in
Range
Also referred to as capture range. This is the input frequency range over which the PLL must be able to pull into
synchronization.
5.8 Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization.
5.9 Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect
to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is
nominally equal to the value of the final output signal or final input signal. Another way of specifying the phase slope
is as the fractional change per time unit. For example; a phase slope of 61
μ
s/s can also be specified as 61 ppm.
5.10 Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
5.11 Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
5.12 Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode
change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to
a steady state.
5.13 Lock Time
This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and
output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).
Lock time is affected by many factors which include:
initial input to output phase difference
initial input to output frequency difference
PLL loop filter bandwidth
PLL phase slope limiter
in-lock phase distance
The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30105 | Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA |
| ZL30105QDG | Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA |
| ZL30106QDG1 | SONET/SDH/PDH Network Interface DPLL |
| ZL30106 | SONET/SDH/PDH Network Interface DPLL |
| ZL30106QDG | SONET/SDH/PDH Network Interface DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30106 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL |
| ZL30106_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL |
| ZL30106QDG | 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Microsemi 功能描述:Microsemi ZL30106QDG Communication Misc |
| ZL30106QDG1 | 制造商:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH NETWORK INTRFC 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE SONET/SDH/PDH NTWK INTERFACEDPLL |
| ZL30107 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:GbE Line Card Synchronizer |
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