參數(shù)資料
型號： ZL30105QDG1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁數(shù)： 42/52頁
文件大?。?/td> 1097K
代理商： ZL30105QDG1
ZL30105
Data Sheet
42
Zarlink Semiconductor Inc.
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
AC Electrical Characteristics* - E1 output timing (see Figure 28).
Characteristics
Sym.
Min.
Max.
Units
Notes
1
C2o delay
t
C2D
-0.4
0.3
ns
outputs loaded
with 30 pF
2
C2o pulse width low
t
C2L
243.0
244.1
ns
3
F4o pulse width low
t
F4L
243.3
244.3
ns
4
F4o delay
t
F4D
121.5
122.2
ns
5
C4o pulse width low
t
C4L
121.0
122.4
ns
6
C4o delay
t
C4D
-0.3
1.1
ns
7
F8o pulse width high
t
F8H
121.6
123.5
ns
8
C8o pulse width low
t
C8L
60.3
61.3
ns
9
C8o delay
t
C8D
-0.4
0.3
ns
10
F16o pulse with low
t
F16L
60.3
61.2
ns
11
F16o delay
t
F16D
29.9
30.8
ns
12
C16o pulse width low
t
C16L
28.7
30.8
ns
13
C16o delay
t
C16D
-0.5
1.5
ns
14
F32o pulse width high
t
F32H
30.0
32.1
ns
15
C32o pulse width low
t
C32L
14.7
15.5
ns
16
C32o delay
t
C32D
-0.5
0.5
ns
17
F65o pulse with low
t
F65L
14.7
15.5
ns
18
F65o delay
t
F65D
7.1
8.0
ns
19
C65o pulse width low
t
C65L
7.2
8.1
ns
20
C65o delay
t
C65D
-1.0
1.0
ns
21
Output clock and frame pulse rise time
t
OR
1.1
2.0
ns
22
Output clock and frame pulse fall time
t
OF
1.2
2.3
ns
相關(guān)PDF資料
PDF描述
ZL30105 Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA
ZL30105QDG Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA
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ZL30106 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/PDH Network Interface DPLL
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