參數(shù)資料
型號: ZL30102QDG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64
文件頁數(shù): 30/50頁
文件大小: 481K
代理商: ZL30102QDG
ZL30102
Data Sheet
30
Zarlink Semiconductor Inc.
Figure 18 - Clock Redundancy with Two Independent Timing Cards
The following is an example of how active/redundant setup can be configured.
The active timing card is set based on the desired application and is set to:
Primary master mode, SEC_MSTR=0
Normal Mode, MODE_SEL1:0=00 (forces device to the input reference set at REF_SEL)
Automatic mode, MODE_SEL1:0=11 (allows device to auto-switch if reference fails)
The HOLDOVER and REF_FAIL pins help evaluate quality of clocks and quality of redundant clock.
The redundant timing card is set based on desired applications and is set to:
Normal (manual) mode, MODE_SEL1:0=00
REF2 and REF2_SYNC as the input reference, REF_SEL1=1 (forces redundant device to lock to output
of active card)
Secondary master mode, SEC_MSTR=1
The HOLDOVER and REF_FAIL pins help evaluate quality of clocks and quality of redundant clock.
Active Timing Card
OSC
ZL30102
BITS 0 clock
BITS 1 clock
Output Clocks
Redundant Timing Card
OSC
ZL30102
Output Clocks
Active Clock
Redundant Clock
REF0
REF1
REF2
REF2_SYNC
REF2
REF2_SYNC
Active Frame Sync (optional)
Redundant Frame Sync (optional)
MODE_SEL1:0=00
REF_SEL1:0=10
SEC_MSTR=1
MODE_SEL1:0=11
SEC_MSTR=0
BITS 0 clock
BITS 1 clock
REF0
REF1
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