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參數(shù)資料
| 型號： | ZL30102QDG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 16/50頁 |
| 文件大?。?/td> | 481K |
| 代理商： | ZL30102QDG |
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ZL30102
Data Sheet
16
Zarlink Semiconductor Inc.
Sync Ratio Monitor (SRM)
: This monitor detects if the REF2_SYNC signal is an 8 kHz signal. It also checks the
number of REF2 reference clock cycles in a single REF2_SYNC frame pulse period to determine the integrity of the
REF2_SYNC signal, for example there must be exactly 256 clock cycles of a 2.048 MHz REF2 reference clock in a
single REF2_SYNC 8 kHz frame pulse period to validate the REF2_SYNC signal. If the REF2 and REF2_SYNC
inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL will abandon the
mechanism of aligning the output frame pulse to the REF2_SYNC pulse. Instead only the REF2 reference will be
used for synchronization.
Figure 7 - REF2_SYNC Reference Monitor
3.3 Time Interval Error (TIE) Corrector Circuit
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the
recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it recovers from Holdover mode.
The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 25. The speed of the phase alignment correction is limited by the selected loop filter bandwidth and the
phase slope limit (see Table 2). Convergence is always in the direction of least phase travel. TIE_CLR can be kept
low continuously; in that case the output clocks will always align with the selected input reference. This is illustrated
in Figure 8.
SYNC
Reference
Monitor
Circuit
to DPLL
REF2_SYNC
REF2
frequency
REF2
相關(guān)PDF資料 |
PDF描述 |
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| ZL30105QDG1 | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105 | Power Clamp On Multimeter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Approval Categories:CAT III 600V; Calibrated:No; Current Measuring Range:0-400.0A; Current Setting AC:400A RoHS Compliant: NA |
| ZL30105QDG | Digital Clamp-On Meter; DMM Type:Clamp; No. of Digits/Alpha:3-3/4; DMM Response Type:True RMS; Calibrated:No; Current Setting AC:1000A; Resistance Measuring Range:400 Ohm to 10 MOhm; Voltage Measuring Range AC:600V RoHS Compliant: NA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30102QDG1 | 制造商:Microsemi Corporation 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE T1/E1 SYSTEM SYNCHRONIZER - Trays |
| ZL30105 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchonizer for AdvancedTCA and H.110 |
| ZL30105_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110 |
| ZL30105QDG | 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Bulk |
| ZL30105QDG1 | 制造商:Microsemi Corporation 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC Pb Free T1/E1 System Synchronizer 制造商:Zarlink Semiconductor Inc 功能描述:CLOCK SYNTHESIZER 64TQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:IC Pb Free T1/E1 System Synchronizer |
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