參數(shù)資料
型號(hào): ZL30102QDG1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
文件頁(yè)數(shù): 32/48頁(yè)
文件大?。?/td> 944K
代理商: ZL30102QDG1
ZL30102
Data Sheet
32
Zarlink Semiconductor Inc.
6.0 Applications
This section contains ZL30102 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
6.1 Power Supply Decoupling
Jitter levels on the ZL30102 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30102 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
6.2 Master Clock
The ZL30102 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30102.
6.2.1 Clock Oscillator
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30102, and the OSCo
output should be left open as shown in Figure 19.
Figure 19 - Clock Oscillator Circuit
1
Frequency
20 MHz
2
Tolerance
as required
3
Rise & fall time
< 10 ns
4
Duty cycle
40% to 60%
Table 7 - Typical Clock Oscillator Specification
+3.3 V
20 MHz OUT
GND
0.1 μF
+3.3 V
OSCo
ZL30102
OSCi
No Connection
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